Steven J. E. Wilton

185 papers A* 2A 26B 32C 3Misc 10Journal 49Unranked 61

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Automated Verilog Assertion Generation Using Fine-Tuned LLMs with Subtask-Specific Iterative Prompting. ISQED Mohammad Shahidzadeh, Behnam Ghavami, Steven J. E. Wilton, Lesley Shannon
2025	Misc	`conf`	Chronbench: An Incremental HDL Benchmark Suite. FCCM Zakary Nafziger, Steven J. E. Wilton
2025	B	`conf`	Open-Source FPGA Routing Runtime Prediction for Improved Productivity Via Smart Route Termination. FPL Andrew David Gunter, Steven J. E. Wilton
2025	A*	`conf`	QUTE: Quantifying Uncertainty in TinyML models with Early-exit-assisted ensembles for model-monitoring. ICML Nikhil Pratap Ghanathe, Steven J. E. Wilton
2025	B	`conf`	Using Data to Reduce Uncertainty in FPGA Routing. FPL Andrew David Gunter, Steven J. E. Wilton
2025	B	`conf`	Versatile Place and Route with Continuous Routing Runtime Prediction and Smart Route Termination. FPL Andrew David Gunter, Steven J. E. Wilton
2024	J	`jnl`	DEBUG-HD: Debugging TinyML models on-device using Hyper-Dimensional computing. CoRR Nikhil Pratap Ghanathe, Steven J. E. Wilton
2024	J	`jnl`	Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors. ACM Trans. Reconfigurable Technol. Syst. Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon
2024	—	`conf`	Enabling Risk Management of Machine Learning Predictions for FPGA Routability. MLCAD Andrew David Gunter, Maya Thomas, Nikhil Pratap Ghanathe, Steven J. E. Wilton
2024	—	`conf`	Machine Learning VLSI CAD Experiments Should Consider Atomic Data Groups. MLCAD Andrew David Gunter, Steven J. E. Wilton
2024	Misc	`conf`	Quantum-Assisted Machine Learning Framework: Training and Evaluation of Boltzmann Machines Using Quantum Annealers. QCE Jose P. Pinilla, Steven J. E. Wilton
2024	Misc	`conf`	Structural Modifications in Quantum-Assisted Training for General Boltzmann Machines. QCE Jose P. Pinilla, Steven J. E. Wilton
2023	Misc	`conf`	A Machine Learning Approach for Predicting the Difficulty of FPGA Routing Problems. FCCM Andrew David Gunter, Steven J. E. Wilton
2023	Misc	`conf`	Designing a configurable IEEE-compliant FPU that supports variable precision for soft processors. FCCM Chris Keilbart, Yuhui Gao, Martin Chua, Eric Matthews, Steven J. E. Wilton, Lesley Shannon
2023	—	`conf`	Online Training from Streaming Data with Concept Drift on FPGAs. ISQED Esther Roorda, Steven J. E. Wilton
2023	A	`conf`	Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems. FPGA Andrew David Gunter, Steven J. E. Wilton
2022	J	`jnl`	Adaptive Clock Management of HLS-generated Circuits on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton
2022	—	`conf`	Boosting Domain-Specific Debug Through Inter-frame Compression. FPT Zakary Nafziger, Martin Chua, Daniel Holanda Noronha, Steven J. E. Wilton
2022	J	`jnl`	FPGA Architecture Exploration for DNN Acceleration. ACM Trans. Reconfigurable Technol. Syst. Esther Roorda, Seyedramin Rasoulinezhad, Philip H. W. Leong, Steven J. E. Wilton
2022	A	`conf`	Positive-Phase Temperature Scaling for Quantum-Assisted Boltzmann Machine Training. SC Jose P. Pinilla, Steven J. E. Wilton
2021	Misc	`conf`	Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs. FCCM Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton
2021	J	`jnl`	In-circuit tuning of deep learning designs. J. Syst. Archit. Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk
2020	J	`jnl`	Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays. ACM Trans. Reconfigurable Technol. Syst. Al-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton
2020	B	`conf`	Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs. FPL Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton
2020	—	`conf`	Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs. FPT Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk
2019	—	`conf`	An Overlay for Rapid FPGA Debug of Machine Learning Applications. FPT Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
2019	C	`conf`	Layout-Aware Embedding for Quantum Annealing Processors. ISC Jose P. Pinilla, Steven J. E. Wilton
2019	A	`conf`	On-chip FPGA Debug Instrumentation for Machine Learning Applications. FPGA Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
2019	A	`conf`	Towards In-Circuit Tuning of Deep Learning Designs. ICCAD Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J. E. Wilton, Wayne Luk
2018	B	`conf`	An FPGA Overlay Architecture Supporting Rapid Implementation of Functional Changes during On-Chip Debug. FPL Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton
2018	A	`conf`	Architecture Exploration for HLS-Oriented FPGA Debug Overlays. FPGA Al-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton
2018	B	`conf`	Extending post-silicon coverage measurement using time-multiplexed FPGA overlays. ETS Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton
2018	J	`jnl`	Introduction to the Special Section on Deep Learning in FPGAs. ACM Trans. Reconfigurable Technol. Syst. Deming Chen, Andrew Putnam, Steven J. E. Wilton
2018	—	`conf`	Kibo: An Open-Source Fixed-Point Tool-kit for Training and Inference in FPGA-Based Deep Learning Networks. IPDPS Workshops Daniel Holanda Noronha, Philip Heng Wai Leong, Steven J. E. Wilton
2018	—	`conf`	LeFlow: Automatic Compilation of TensorFlow Machine Learning Applications to FPGAs. FPT Daniel Holanda Noronha, Kahlan Gibson, Bahar Salehpour, Steven J. E. Wilton
2018	J	`jnl`	LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks. CoRR Daniel H. Noronha, Bahar Salehpour, Steven J. E. Wilton
2018	J	`jnl`	Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug. ACM Trans. Design Autom. Electr. Syst. Fatemeh Eslami, Steven J. E. Wilton
2018	—	`conf`	Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques. FPT Siddhartha, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong
2017	B	`conf`	Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. FPL Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton
2017	—	`conf`	Rapid circuit-specific inlining tuning for FPGA high-level synthesis. ReConFig Daniel H. Noronha, Jose P. Pinilla, Steven J. E. Wilton
2017	J	`jnl`	Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeffrey Goeders, Steven J. E. Wilton
2016	J	`jnl`	An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating. IEEE Trans. Very Large Scale Integr. Syst. Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk
2016	J	`jnl`	An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug. SIGARCH Comput. Archit. News Fatemeh Eslami, Steven J. E. Wilton
2016	J	`jnl`	Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges. CoRR Fatemeh Eslami, Eddie Hung, Steven J. E. Wilton
2016	—	`conf`	Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs. FPT Jose P. Pinilla, Steven J. E. Wilton
2016	B	`conf`	Quantifying observability for in-system debug of high-level synthesis circuits. FPL Jeffrey Goeders, Steven J. E. Wilton
2016	—	`conf`	RAW Introduction and Committees. IPDPS Workshops Marco D. Santambrogio, Ramachandran Vaidyanathan, Diana Goehringer, Steven J. E. Wilton
2016	—	`ch.`	Systems-on-Chip on FPGAs. FPGAs for Software Programmers Jeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton
2015	J	`jnl`	Allowing Software Developers to Debug HLS Hardware. CoRR Jeffrey B. Goeders, Steven J. E. Wilton
2015	—	`conf`	An adaptive virtual overlay for fast trigger insertion for FPGA debug. FPT Fatemeh Eslami, Steven J. E. Wilton
2015	—	`conf`	Hierarchical Dynamic Power-Gating in FPGAs. ARC Rehan Ahmed, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas
2015	—	`conf`	RAW Introduction and Committees. IPDPS Workshops Jürgen Becker, Ken Eguro, Diana Göhringer, Wayne Luk, Marco D. Santambrogio, Ramachandran Vaidyanathan, Steven J. E. Wilton
2015	Misc	`conf`	Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. FCCM Jeffrey B. Goeders, Steven J. E. Wilton
2015	—	`conf`	Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs. FPT Jeffrey Goeders, Steven J. E. Wilton
2014	J	`jnl`	A Configurable Architecture to Limit Inrush Current in Power-Gated Reconfigurable Devices. J. Low Power Electron. Assem A. M. Bsoul, Steven J. E. Wilton
2014	J	`jnl`	Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. ACM Trans. Design Autom. Electr. Syst. Eddie Hung, Steven J. E. Wilton
2014	B	`conf`	Effective FPGA debug for high-level synthesis generated circuits. FPL Jeffrey B. Goeders, Steven J. E. Wilton
2014	—	`conf`	Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry. ARC Eddie Hung, Jeffrey B. Goeders, Steven J. E. Wilton
2014	B	`conf`	High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs. FPL Rehan Ahmed, Assem A. M. Bsoul, Steven J. E. Wilton, Peter Hallschmid, Richard Klukas
2014	J	`jnl`	Incremental Trace-Buffer Insertion for FPGA Debug. IEEE Trans. Very Large Scale Integr. Syst. Eddie Hung, Steven J. E. Wilton
2014	B	`conf`	Incremental distributed trigger insertion for efficient FPGA debug. FPL Fatemeh Eslami, Steven J. E. Wilton
2014	J	`jnl`	Power Aware Architecture Exploration for Field Programmable Gate Arrays. J. Low Power Electron. Jeffrey B. Goeders, Steven J. E. Wilton
2013	Misc	`conf`	Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices. FCCM Eddie Hung, Fatemeh Eslami, Steven J. E. Wilton
2013	J	`jnl`	Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics. IEEE Des. Test Eddie Hung, Bradley R. Quinton, Steven J. E. Wilton
2013	—	`conf`	Maximum flow algorithms for maximum observability during FPGA debug. FPT Eddie Hung, Al-Shahna Jamal, Steven J. E. Wilton
2013	J	`jnl`	Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs. IEEE Trans. Computers Kyle Balston, Mehdi Karimibiuki, Alan J. Hu, André Ivanov, Steven J. E. Wilton
2013	J	`jnl`	Scalable Signal Selection for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. Eddie Hung, Steven J. E. Wilton
2013	J	`jnl`	Towards development of an analytical model relating FPGA architecture parameters to routability. ACM Trans. Reconfigurable Technol. Syst. Joydip Das, Steven J. E. Wilton
2013	A	`conf`	Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers. FPGA Eddie Hung, Steven J. E. Wilton
2012	A	`conf`	A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. FPGA Assem A. M. Bsoul, Steven J. E. Wilton
2012	—	`conf`	Advances in 3D design and optimization. CICC Steven J. E. Wilton, Visvesh S. Sathe
2012	—	`conf`	An FPGA with power-gated switch blocks. FPT Assem A. M. Bsoul, Steven J. E. Wilton
2012	—	`conf`	Emulation in post-silicon validation: It's not just for functionality anymore. HLDVT Kyle Balston, Alan J. Hu, Steven J. E. Wilton, Amir Nahir
2012	J	`jnl`	Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang
2012	J	`jnl`	Hierarchical Benchmark Circuit Generation for FPGA Architecture Evaluation. ACM Trans. Embed. Comput. Syst. Cindy Mark, Scott Y. L. Chin, Lesley Shannon, Steven J. E. Wilton
2012	B	`conf`	Limitations of incremental signal-tracing for FPGA debug. FPL Eddie Hung, Steven J. E. Wilton
2012	J	`jnl`	Multi-objective voltage island floorplanning using sequence pair representation. Sustain. Comput. Informatics Syst. Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov
2012	J	`jnl`	Optimizing Floating Point Units in Hybrid FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton
2012	—	`conf`	Rapid RTL-based signal ranking for FPGA prototyping. FPT Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung
2012	—	`conf`	VersaPower: Power estimation for diverse FPGA architectures. FPT Jeffrey B. Goeders, Steven J. E. Wilton
2011	—	`conf`	Accelerated FPGA architecture design: Capabilities and limitations of analytical models. FPT Joydip Das, Steven J. E. Wilton
2011	J	`jnl`	An Analytical Model Relating FPGA Architecture to Logic Density and Depth. IEEE Trans. Very Large Scale Integr. Syst. Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2011	A	`conf`	An analytical model relating FPGA architecture parameters to routability. FPGA Joydip Das, Steven J. E. Wilton
2011	—	`conf`	Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton
2011	—	`conf`	On evaluating signal selection algorithms for post-silicon debug. ISQED Eddie Hung, Steven J. E. Wilton
2011	J	`jnl`	Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. Very Large Scale Integr. Syst. Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton
2011	—	`conf`	Sequence pair based voltage island floorplanning. IGCC Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh
2011	B	`conf`	Speculative Debug Insertion for FPGAs. FPL Eddie Hung, Steven J. E. Wilton
2011	A	`conf`	Towards scalable FPGA CAD through architecture. FPGA Scott Y. L. Chin, Steven J. E. Wilton
2010	—	`conf`	Accelerating trace computation in post-silicon debug. ISQED Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt
2010	—	`conf`	An FPGA architecture supporting dynamically controlled power gating. FPT Assem A. M. Bsoul, Steven J. E. Wilton
2010	J	`jnl`	Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward
2010	A	`conf`	The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton
2010	—	`conf`	Towards Analytical Methods for FPGA Architecture Investigation. ARC Steven J. E. Wilton
2009	—	`conf`	A detailed delay path model for FPGAs. FPT Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong
2009	B	`conf`	An analytical model relating FPGA architecture and place and route runtime. FPL Scott Y. L. Chin, Steven J. E. Wilton
2009	—	`conf`	Charge-borrowing decap: A novel circuit for removal of local supply noise violations. CICC Xiongfei Meng, Resve A. Saleh, Steven J. E. Wilton
2009	—	`conf`	Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung
2009	J	`jnl`	Floating-Point FPGA: Architecture and Modeling. IEEE Trans. Very Large Scale Integr. Syst. Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2009	B	`conf`	Improving the memory footprint and runtime scalability of FPGA CAD algorithms. FPL Scott Y. L. Chin, Steven J. E. Wilton
2009	B	`conf`	Modeling post-techmapping and post-clustering FPGA circuit depth. FPL Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2009	J	`jnl`	Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. Bradley R. Quinton, Steven J. E. Wilton
2009	—	`conf`	Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. SoCC Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward
2009	—	`conf`	Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms. SoC Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward
2009	J	`jnl`	Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms. ACM Trans. Reconfigurable Technol. Syst. Scott Y. L. Chin, Steven J. E. Wilton
2009	A	`conf`	Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. FPGA Alastair M. Smith, Steven J. E. Wilton, Joydip Das
2008	J	`jnl`	A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. ACM Trans. Reconfigurable Technol. Syst. Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk
2008	—	`conf`	A system-level stochastic circuit generator for FPGA architecture evaluation. FPT Cindy Mark, Ava Shui, Steven J. E. Wilton
2008	B	`conf`	An analytical model describing the relationships between logic architecture and FPGA density. FPL Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2008	B	`conf`	BackSpace: Formal Analysis for Post-Silicon Debug. FMCAD Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton, Jin Yang
2008	—	`conf`	BackSpace: Moving Towards Reality. MTV Flavio M. de Paula, Marcel Gort, Alan J. Hu, Steven J. E. Wilton
2008	—	`ch.`	Field-Programmable Gate Array Architectures. Handbook of Algorithms for Physical Design Automation Steven J. E. Wilton, Nathalie Chan King Choy, Scott Y. L. Chin, Kara K. W. Poon
2008	J	`jnl`	GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. Very Large Scale Integr. Syst. Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
2008	J	`jnl`	On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays. Int. J. Reconfigurable Comput. Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton
2008	J	`jnl`	On the trade-off between power and flexibility of FPGA clock networks. ACM Trans. Reconfigurable Technol. Syst. Julien Lamoureux, Steven J. E. Wilton
2008	—	`conf`	Optimizing coarse-grained units in floating point hybrid FPGA. FPT Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton
2008	J	`jnl`	Practical Asynchronous Interconnect Network Design. IEEE Trans. Very Large Scale Integr. Syst. Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton
2008	B	`conf`	Rapid estimation of power consumption for hybrid FPGAs. FPL Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2008	—	`conf`	Session 14 - Advanced SoCs - techniques and applications. CICC Steven J. E. Wilton, Arif Rahman
2008	J	`jnl`	The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. Int. J. Reconfigurable Comput. Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2007	A	`conf`	A synthesizable datapath-oriented embedded FPGA fabric. FPGA Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton
2007	B	`conf`	Clock-Aware Placement for FPGAs. FPL Julien Lamoureux, Steven J. E. Wilton
2007	B	`conf`	Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. FPL Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2007	B	`conf`	Embedded Programmable Logic Core Enhancements for System Bus Interfaces. FPL Bradley R. Quinton, Steven J. E. Wilton
2007	A	`conf`	GlitchLess: an active glitch minimization technique for FPGAs. FPGA Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
2007	—	`conf`	Memory Footprint Reduction for FPGA Routing Algorithms. FPT Scott Y. L. Chin, Steven J. E. Wilton
2006	B	`conf`	Activity Estimation for Field-Programmable Gate Arrays. FPL Julien Lamoureux, Steven J. E. Wilton
2006	—	`conf`	Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs. FPT Nathalie Chan King Choy, Steven J. E. Wilton
2006	B	`conf`	Architecture and CAD for FPGA Clock Networks. FPL Julien Lamoureux, Steven J. E. Wilton
2006	A	`conf`	FPGA clock network architecture: flexibility vs. area and power. FPGA Julien Lamoureux, Steven J. E. Wilton
2006	B	`conf`	Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. FPL Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton
2006	A	`ed.`	Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA 2006, Monterey, California, USA, February 22-24, 2006 FPGA Steven J. E. Wilton, André DeHon
2006	J	`jnl`	Product-Term-Based Synthesizable Embedded Programmable Logic Cores. IEEE Trans. Very Large Scale Integr. Syst. Andy Yan, Steven J. E. Wilton
2006	J	`jnl`	System-on-Chip: Reuse and Integration. Proc. IEEE Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov
2006	Misc	`conf`	Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo
2005	J	`jnl`	A detailed power model for field-programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. Kara K. W. Poon, Steven J. E. Wilton, Andy Yan
2005	J	`jnl`	A novel FPGA architecture supporting wide, shallow memories. IEEE Trans. Very Large Scale Integr. Syst. Steven W. Oldridge, Steven J. E. Wilton
2005	—	`conf`	Advances in programmable logic. CICC Steven J. E. Wilton, Albert Stritter
2005	C	`conf`	Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. ICCD Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton
2005	A	`conf`	Challenges and opportunities for low power FPGAs in nanometer technologies. ISLPED Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton
2005	—	`conf`	Concentrator access networks for programmable logic cores on SoCs. ISCAS (1) Bradley R. Quinton, Steven J. E. Wilton
2005	J	`jnl`	Design considerations for soft embedded programmable logic cores. IEEE J. Solid State Circuits Steven J. E. Wilton, Noha Kafafi, James C. H. Wu, Kimberly A. Bozman, Victor O. Aken'Ova, Resve Saleh
2005	—	`conf`	Dynamic Voltage Scaling for Commercial FPGAs. FPT Gary Chun Tak Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2005	J	`jnl`	On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. J. Low Power Electron. Julien Lamoureux, Steven J. E. Wilton
2005	—	`conf`	Post-Silicon Debug Using Programmable Logic Cores. FPT Bradley R. Quinton, Steven J. E. Wilton
2005	B	`ed.`	Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005 FPL Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong
2005	A	`ed.`	Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005 FPGA Herman Schmit, Steven J. E. Wilton
2005	Misc	`conf`	Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. FCCM Zion S. Kwok, Steven J. E. Wilton
2005	J	`jnl`	Routing architecture optimizations for high-density embedded programmable IP cores. IEEE Trans. Very Large Scale Integr. Syst. Peter Hallschmid, Steven J. E. Wilton
2004	—	`conf`	An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. ISCAS (2) Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux
2004	—	`conf`	Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. FPT Steven J. E. Wilton, Noha Kafafi, Bingfeng Mei, Serge Vernalde
2004	—	`conf`	Placement and routing for non-rectangular embedded programmable logic cores in SoC design. FPT Tony Wong, Steven J. E. Wilton
2004	—	`conf`	Sequential synthesizable embedded programmable logic cores for system-on-chip. CICC Andy Yan, Steven J. E. Wilton
2004	B	`conf`	The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. FPL Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
2003	A	`conf`	Architectures and algorithms for synthesizable embedded programmable logic cores. FPGA Noha Kafafi, Kimberly A. Bozman, Steven J. E. Wilton
2003	A	`conf`	On the Interaction Between Power-Aware FPGA CAD Algorithms. ICCAD Julien Lamoureux, Steven J. E. Wilton
2003	—	`conf`	Placement and routing for FPGA architectures supporting wide shallow memories. FPT Steven W. Oldridge, Steven J. E. Wilton
2003	—	`conf`	Product-term based synthesizable embedded programmable logic cores. FPT Andy Yan, Steven J. E. Wilton
2003	—	`conf`	SoC implementation issues for synthesizable embedded programmable logic cores. CICC James C. H. Wu, Victor O. Aken'Ova, Steven J. E. Wilton, Resve A. Saleh
2002	B	`conf`	A Flexible Power Model for FPGAs. FPL Kara K. W. Poon, Andy Yan, Steven J. E. Wilton
2002	—	`conf`	Implementing logic in FPGA memory arrays: heterogeneous memory architectures. FPT Steven J. E. Wilton
2002	A	`conf`	On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. FPGA Andy Yan, Rebecca Cheng, Steven J. E. Wilton
2002	—	`conf`	Sensitivity of FPGA power evaluation. FPT Kara K. W. Poon, Steven J. E. Wilton
2002	—	`conf`	The architecture of dual-mode FPGA embedded system blocks. CICC Ernie Lin, Steven J. E. Wilton
2001	A	`conf`	A crosstalk-aware timing-driven router for FPGAs. FPGA Steven J. E. Wilton
2001	—	`conf`	A novel FPGA architecture supporting wide shallow memories. CICC Steven W. Oldridge, Steven J. E. Wilton
2001	A	`conf`	Detailed routing architectures for embedded programmable logic IP cores. FPGA Peter Hallschmid, Steven J. E. Wilton
2001	B	`conf`	Macrocell Architectures for Product Term Embedded Memory Arrays. FPL Ernie Lin, Steven J. E. Wilton
2001	—	`conf`	Programmable logic IP cores in SoC design: opportunities and challenges. CICC Steven J. E. Wilton, Resve Saleh
2001	J	`jnl`	Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. Very Large Scale Integr. Syst. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
2000	—	`conf`	Architecture of cluster-based FPGAs with memory. CICC Jason P. Clifford, Steven J. E. Wilton
2000	B	`conf`	FPGA Implementation of a Prototype WDM On-Line Scheduler. FPL Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh
2000	A	`conf`	Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. FPGA Steven J. E. Wilton
2000	J	`jnl`	Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Steven J. E. Wilton
1999	B	`conf`	A New Switch Block for Segmented FPGAs. FPL M. Imran Masud, Steven J. E. Wilton
1999	B	`conf`	Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. FPL William K. C. Ho, Steven J. E. Wilton
1999	J	`jnl`	The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. Very Large Scale Integr. Syst. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
1998	—	`conf`	Implementing logic in FPGA embedded memory arrays: architectural implications. CICC Steven J. E. Wilton
1998	A	`conf`	SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. FPGA Steven J. E. Wilton
1997	A	`conf`	Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
1996	J	`jnl`	CACTI: an enhanced cache access and cycle time model. IEEE J. Solid State Circuits Steven J. E. Wilton, Norman P. Jouppi
1995	A	`conf`	Architecture of Centralized Field-Configurable Memory. FPGA Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
1994	A*	`conf`	Tradeoffs in Two-Level On-Chip Caching. ISCA Norman P. Jouppi, Steven J. E. Wilton
1993	C	`conf`	A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton
1993	—	`conf`	Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. SPDP Steven J. E. Wilton, Zvonko G. Vranesic