Steven H. Voldman

12 papers Journal 10Unranked 2
YearRankTypeTitle / Venue / Authors
2023 J jnl
Computational Simulation of a Field-Induced Charged Board Event Test Bench Using Transient Analysis.
IEEE Access
S. Chumpen, S. Pimpakun, S. Plong-Ngooluam, Steven H. Voldman, Chiranut Sa-ngiamsak
2015 — conf
Electrical Overstress (EOS): Challenges for component and system-level co-design.
ASICON
Steven H. Voldman
2005 J jnl
A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II - Latchup.
Microelectron. Reliab.
Steven H. Voldman
2005 J jnl
A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I - ESD.
Microelectron. Reliab.
Steven H. Voldman
2005 — conf
ESD-Induced Internal Core Device Failure: New Failure Modes in System-on-Chip (SoC) Designs, invited.
IWSOC
Yoon Huh, Peter Bendix, Kyungjin Min, Jau-Wen Chen, Ravindra Narayan, Larry D. Johnson, Steven H. Voldman
2004 J jnl
A review of electrostatic discharge (ESD) in advanced semiconductor technology.
Microelectron. Reliab.
Steven H. Voldman
2003 J jnl
Foundation of rf CMOS and SiGe BiCMOS technologies.
IBM J. Res. Dev.
James S. Dunn, David C. Ahlgren, Douglas D. Coolbaugh, Natalie B. Feilchenfeld, Greg G. Freeman, David R. Greenberg, Robert A. Groves, Fernando J. Guarín, Youssef Hammad, Alvin J. Joseph, Louis D. Lanzerotti, Stephen A. St. Onge, Bradley A. Orner, Jae-Sung Rieh, Kenneth J. Stein, Steven H. Voldman, Ping-Chuan Wang, Michael J. Zierak, Seshadri Subbanna, David L. Harame, Dean A. Herman Jr., Bernard S. Meyerson
2003 J jnl
Microanalysis and electromigration reliability performance of high current transmission line pulse (TLP) stressed copper interconnects.
Microelectron. Reliab.
Sherry Suat Cheng Khoo, Pee Ya Tan, Steven H. Voldman
2001 J jnl
A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies.
Microelectron. Reliab.
Steven H. Voldman, W. Anderson, R. Ashton, M. Chaine, Charvaka Duvvury, T. Maloney, E. Worley
1999 J jnl
The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling.
IEEE J. Solid State Circuits
Steven H. Voldman
1995 J jnl
Overview of gate linewidth control in the manufacture of CMOS logic chips.
IBM J. Res. Dev.
Donald G. Chesebro, James W. Adkisson, Lyman R. Clark, Steven N. Eslinger, Margaret A. Faucher, Steven J. Holmes, Raymond P. Mallette, Edward J. Nowak, Edward W. Sengle, Steven H. Voldman, Thomas W. Weeks
1995 J jnl
The evolution of IBM CMOS DRAM technology.
IBM J. Res. Dev.
Eric Adler, John K. DeBrosse, Stephen F. Geissler, Steven J. Holmes, Mark D. Jaffe, Jeffrey B. Johnson, Charles W. Koburger III, Jerome B. Lasky, Brian Lloyd, Glen L. Miles, James S. Nakos, Wendell P. Noble Jr., Steven H. Voldman, Michael Armacost, Richard Ferguson