Steven Derrien

86 papers A* 5A 12B 9C 5Misc 6Journal 24Unranked 23

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Ahead of Time Generation for GPSA Protection in RISC-V Embedded Cores. ASAP Louis Savary, Simon Rokicki, Steven Derrien
2025	A	`conf`	Hardware/Software Runtime for GPSA Protection in RISC-V Embedded Cores. DATE Louis Savary, Simon Rokicki, Steven Derrien
2025	A*	`conf`	Optimizing Recovery Logic in Speculative High-Level Synthesis. DAC Dylan Leothaud, Jean-Michel Gorius, Simon Rokicki, Steven Derrien
2024	B	`conf`	A Unified Memory Dependency Framework for Speculative High-Level Synthesis. CC Jean-Michel Gorius, Simon Rokicki, Steven Derrien
2024	J	`jnl`	An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators. CoRR Corentin Ferry, Nicolas Derumigny, Steven Derrien, Sanjay V. Rajopadhye
2024	B	`conf`	Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis. FPL Dylan Leothaud, Jean-Michel Gorius, Simon Rokicki, Steven Derrien
2023	J	`jnl`	An Irredundant Decomposition of Data Flow with Affine Dependences. CoRR Corentin Ferry, Steven Derrien, Sanjay V. Rajopadhye
2023	B	`conf`	Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations. PACT Louis Narmour, Steven Derrien, Sanjay V. Rajopadhye
2023	J	`jnl`	Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Corentin Ferry, Tomofumi Yuki, Steven Derrien, Sanjay V. Rajopadhye
2023	—	`conf`	Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis. ARC Sara Sadat Hoseininasab, Caroline Collange, Steven Derrien
2022	—	`conf`	Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis. FPT Jean-Michel Gorius, Simon Rokicki, Steven Derrien
2022	J	`jnl`	Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout. CoRR Corentin Ferry, Tomofumi Yuki, Steven Derrien, Sanjay V. Rajopadhye
2022	J	`jnl`	Maximal Atomic irRedundant Sets: a Usage-based Dataflow Partitioning Algorithm. CoRR Corentin Ferry, Steven Derrien, Sanjay V. Rajopadhye
2022	J	`jnl`	SpecHLS: Speculative Accelerator Design Using High-Level Synthesis. IEEE Micro Jean-Michel Gorius, Simon Rokicki, Steven Derrien
2022	J	`jnl`	Special Issue on Applied Reconfigurable Computing. J. Signal Process. Syst. Frank Hannig, Steven Derrien
2021	—	`ed.`	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings ARC Steven Derrien, Frank Hannig, Pedro C. Diniz, Daniel Chillet
2020	J	`jnl`	Application-Specific Arithmetic in High-Level Synthesis Tools. ACM Trans. Archit. Code Optim. Yohann Uguen, Florent de Dinechin, Victor Lezaud, Steven Derrien
2020	J	`jnl`	Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Thibaut Marty, Tomofumi Yuki, Steven Derrien
2020	J	`jnl`	Toward Speculative Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Steven Derrien, Thibaut Marty, Simon Rokicki, Tomofumi Yuki
2019	A	`conf`	Aggressive Memory Speculation in HW/SW Co-Designed Machines. DATE Simon Rokicki, Erven Rohou, Steven Derrien
2019	B	`conf`	Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures. ECRTS Benjamin Rouxel, Stefanos Skalistis, Steven Derrien, Isabelle Puaut
2019	J	`jnl`	Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Simon Rokicki, Erven Rohou, Steven Derrien
2019	A	`conf`	Reconciling Compiler Optimizations and WCET Estimation Using Iterative Compilation. RTSS Mickaël Dardaillon, Stefanos Skalistis, Isabelle Puaut, Steven Derrien
2019	J	`jnl`	Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications. J. Aerosp. Inf. Syst. Simon Reder, Fabian Kempf, Harald Bucher, Jürgen Becker, Panayiotis Alefragis, Nikolaos S. Voros, Stefanos Skalistis, Steven Derrien, Isabelle Puaut, Oliver Oey, Timo Stripf, Christian Ferdinand, Clément David, Peer Ulbig, David Müller, Umut Durak
2018	—	`conf`	Enabling Overclocking Through Algorithm-Level Error Detection. FPT Thibaut Marty, Tomofumi Yuki, Steven Derrien
2018	—	`conf`	Fine-Grain Iterative Compilation for WCET Estimation. WCET Isabelle Puaut, Mickaël Dardaillon, Christoph Cullmann, Gernot Gebhard, Steven Derrien
2018	A	`conf`	Supporting runtime reconfigurable VLIWs cores through dynamic binary translation. DATE Simon Rokicki, Erven Rohou, Steven Derrien
2018	A	`conf`	Using polyhedral techniques to tighten WCET estimates of optimized code: A case study with array contraction. DATE Thomas Lefeuvre, Imen Fassi, Christoph Cullmann, Gernot Gebhard, Emin-Koray Kasnakli, Isabelle Puaut, Steven Derrien
2017	Misc	`conf`	A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators. FCCM Yohann Uguen, Florent de Dinechin, Steven Derrien
2017	B	`conf`	Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations. FPL Yohann Uguen, Florent de Dinechin, Steven Derrien
2017	J	`jnl`	Foreword to the Special Section on Reconfigurable Computing. J. Signal Process. Syst. Steven Derrien, Kubilay Atasu, João M. P. Cardoso, Jürgen Becker
2017	A	`conf`	Hardware-accelerated dynamic binary translation. DATE Simon Rokicki, Erven Rohou, Steven Derrien
2017	B	`conf`	One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs. FPL Gaël Deest, Tomofumi Yuki, Sanjay V. Rajopadhye, Steven Derrien
2017	A	`conf`	Superword level parallelism aware word length optimization. DATE Ali Hassan El Moussawi, Steven Derrien
2017	J	`jnl`	Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures. ACM Trans. Embed. Comput. Syst. Benjamin Rouxel, Steven Derrien, Isabelle Puaut
2017	A	`conf`	WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. DATE Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker
2016	—	`conf`	Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures. MCSoC Baptiste Roux, Matthieu Gautier, Olivier Sentieys, Steven Derrien
2016	—	`conf`	Demo: SLP-aware word length optimization. DASIP Ali Hassan El Moussawi, Steven Derrien
2016	A	`conf`	System level synthesis for virtual memory enabled hardware threads. DATE Nicolas Estibals, Gaël Deest, Ali Hassan El Moussawi, Steven Derrien
2015	J	`jnl`	Combining execution pipelines to improve parallel implementation of HMMER on FPGA. Microprocess. Microsystems Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton, Alexandre Cornu, Dominique Lavenier
2014	J	`jnl`	Component reuse methodology for multi-clock Data-Flow parallel embedded Systems. ARIMA J. Anne-Marie Chana, Patrice Quinton, Steven Derrien
2014	Misc	`conf`	Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes. FCCM Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien, Christophe Huriaux
2014	A	`conf`	Toward scalable source level accuracy analysis for floating-point to fixed-point conversion. ICCAD Gaël Deest, Tomofumi Yuki, Olivier Sentieys, Steven Derrien
2013	J	`jnl`	Compiling Scilab to high performance embedded multicore systems. Microprocess. Microsystems Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, Thomas Perschke
2013	C	`conf`	Component-Level Datapath Merging in System-Level Design of Wireless Sensor Node Controllers for FPGA-Based Implementations. DSD Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
2013	—	`conf`	Derivation of efficient FSM from loop nests. FPT Tomofumi Yuki, Antoine Morvan, Steven Derrien
2013	C	`conf`	GeCoS: A framework for prototyping custom hardware design flows. SCAM Antoine Floch, Tomofumi Yuki, Ali El Moussawi, Antoine Morvan, Kevin J. M. Martin, Maxime Naullet, Mythri Alle, Ludovic L'Hours, Nicolas Simon, Steven Derrien, François Charot, Christophe Wolinski, Olivier Sentieys
2013	J	`jnl`	Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Antoine Morvan, Steven Derrien, Patrice Quinton
2013	A*	`conf`	Runtime dependency analysis for loop pipelining in high-level synthesis. DAC Mythri Alle, Antoine Morvan, Steven Derrien
2013	B	`conf`	Using Model Types to Support Contract-Aware Model Substitutability. ECMFA Wuliang Sun, Benoît Combemale, Steven Derrien, Robert B. France
2012	—	`conf`	A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems. CSE Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Jordy Potman, Kim Sunesen, Steven Derrien, Olivier Sentieys, Jürgen Becker
2012	—	`conf`	A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. ReCoSoC Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Ménard, Olivier Sentieys, Diana Göhringer, Thomas Perschke
2012	A*	`conf`	A semiempirical model for wakeup time estimation in power-gated logic clusters. DAC Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien
2012	J	`jnl`	Bridging the chasm between MDE and the world of compilation. Softw. Syst. Model. Jean-Marc Jézéquel, Benoît Combemale, Steven Derrien, Clément Guy, Sanjay V. Rajopadhye
2012	—	`conf`	Efficient hardware implementation of data-flow parallel embedded systems. ICSAMOS Patrice Quinton, Anne-Marie Chana, Steven Derrien
2012	C	`conf`	From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. DSD Jürgen Becker, Timo Stripf, Oliver Oey, Michael Hübner, Steven Derrien, Daniel Ménard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Göhringer
2012	—	`conf`	From Scilab to multicore embedded systems: Algorithms and methodologies. ICSAMOS George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Göhringer, Steven Derrien, Daniel Ménard, Olivier Sentieys, Michael Hübner, Timo Stripf, Oliver Oey, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas
2012	B	`conf`	On Model Subtyping. ECMFA Clément Guy, Benoît Combemale, Steven Derrien, Jim Steel, Jean-Marc Jézéquel
2012	J	`jnl`	System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow. ACM Trans. Design Autom. Electr. Syst. Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
2011	J	`jnl`	A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters. J. Low Power Electron. Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien
2011	—	`book`	Contributions à la conception d'architectures matérielles dédiées. Steven Derrien
2011	—	`conf`	Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion. FPT Antoine Morvan, Steven Derrien, Patrice Quinton
2011	—	`conf`	HLS Tools for FPGA: Faster Development with Better Performance. ARC Alexandre Cornu, Steven Derrien, Dominique Lavenier
2011	A	`conf`	Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far? MoDELS Antoine Floch, Tomofumi Yuki, Clément Guy, Steven Derrien, Benoît Combemale, Sanjay V. Rajopadhye, Robert B. France
2011	Misc	`conf`	Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters. VLSI Design Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien
2011	—	`conf`	ompVerify: Polyhedral Analysis for the OpenMP Programmer. IWOMP V. Basupalli, Tomofumi Yuki, Sanjay V. Rajopadhye, Antoine Morvan, Steven Derrien, Patrice Quinton, David Wonnacott
2010	A*	`conf`	A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking. DAC Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
2010	—	`conf`	Accelerating HMMER on FPGA using parallel prefixes and reductions. FPT Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton
2010	J	`jnl`	Hardware Acceleration of HMMER on FPGAs. J. Signal Process. Syst. Steven Derrien, Patrice Quinton
2010	C	`conf`	System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes. DSD Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
2009	C	`conf`	Ultra Low-power FSM for Control Oriented Applications. ISCAS Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
2008	J	`jnl`	Deriving efficient control in Process Networks with Compaan/Laura. Int. J. Embed. Syst. Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere
2007	—	`conf`	Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval. ARC Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton
2007	—	`conf`	Parallelizing HMMER for Hardware Acceleration on FPGAs. ASAP Steven Derrien, Patrice Quinton
2006	A	`conf`	Acceleration of a content-based image-retrieval application on the RDISK cluster. IPDPS Auguste Noumsi, Steven Derrien, Patrice Quinton
2005	J	`jnl`	Cluster of re-configurable nodes for scanning large genomic banks. Parallel Comput. Stéphane Guyetant, Mathieu Giraud, Ludovic L'Hours, Steven Derrien, Stéphane Rubini, Dominique Lavenier, Frédéric Raimbault
2005	—	`conf`	Hardware/Software Interface for Multi-Dimensional Processor Arrays. ASAP Alain Darte, Steven Derrien, Tanguy Risset
2003	—	`conf`	A Reconfigurable Parallel Disk System for Filtering Genomic Banks. Engineering of Reconfigurable Systems and Algorithms Dominique Lavenier, Stéphane Guyetant, Steven Derrien, Stéphane Rubini
2002	—	`conf`	Energy/Power Estimation of Regular Processor Arrays. ISSS Sanjay V. Rajopadhye, Steven Derrien
2001	—	`conf`	Combined instruction and loop parallelism in array synthesis for FPGAs. ISSS Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
2001	Misc	`conf`	Combining Instruction and Loop Level Parallelism for FPGAs. FCCM Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay
2001	B	`conf`	Loop Tiling for Reconfigurable Accelerators. FPL Steven Derrien, Sanjay V. Rajopadhye
2000	A*	`conf`	Approximating a Single Viewpoint in Panoramic Imaging Devices. ICRA Steven Derrien, Kurt Konolige
2000	Misc	`conf`	FCCMS and the Memory Wall. FCCM Steven Derrien, Sanjay V. Rajopadhye
2000	Misc	`conf`	Interfacing compiled FPGA programs: the MMAlpha approach. PDPTA Steven Derrien, Tanguy Risset
2000	—	`conf`	Optimal Partitioning for FPGA Based Regular Array Implementations. PARELEC Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay