Stephen V. Kosonocky

23 papers A* 2A 5C 1Misc 2Journal 6Unranked 7

Year	Rank	Type	Title / Venue / Authors
2014	—	`conf`	5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. ISSCC Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox
2010	J	`jnl`	Are you having fun yet? IEEE Des. Test Comput. Stephen V. Kosonocky
2008	A*	`conf`	Keeping hot chips cool: are IC thermal problems hot air? DAC Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul D. Franzon, Andrew Yang, Stephen V. Kosonocky
2007	J	`jnl`	A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, Marios C. Papaefthymiou
2007	A*	`conf`	Early Power-Aware Design & Validation: Myth or Reality? DAC Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis
2007	J	`jnl`	Introduction to the Special Issue on the 2006 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Stephen V. Kosonocky, Kazuo Yano
2007	—	`conf`	Multi-Dimensional Circuit and Micro-Architecture Level Optimization. ISQED Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan
2007	—	`conf`	Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan
2005	J	`jnl`	Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. Integr. Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
2004	—	`conf`	A synchronous interface for SoCs with multiple clock domains. SoCC Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky
2004	—	`conf`	Characterization of logic circuit techniques for high leakage CMOS technologies. ACM Great Lakes Symposium on VLSI Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
2004	A	`conf`	Experimental measurement of a novel power gating structure with intermediate power saving mode. ISLPED Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz
2003	J	`jnl`	Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. IBM J. Res. Dev. Jean-Olivier Plouchart, Noah Zamdmer, Jonghae Kim, Melanie Sherony, Yue Tan, Asit Ray, Mohamed Talbi, Lawrence F. Wagner, Kun Wu, Naftali E. Lustig, Shreesh Narasimha, Patricia O'Neil, Nghia Phan, Michael Rohn, James Strom, David M. Friend, Stephen V. Kosonocky, Daniel R. Knebel, Suhwan Kim, Keith A. Jenkins, Michel M. Rivier
2003	J	`jnl`	Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban
2003	—	`conf`	Minimizing inductive noise in system-on-a-chip with multiple power gating structures. ESSCIRC Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, David F. Heidel, Michael Immediato
2003	A	`conf`	Understanding and minimizing ground bounce during mode transition of power gating structures. ISLPED Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel
2002	A	`conf`	Low power integrated scan-retention mechanism. ISLPED Victor V. Zyuban, Stephen V. Kosonocky
2002	—	`conf`	Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits. ISVLSI Alice Wang, Anantha P. Chandrakasan, Stephen V. Kosonocky
2001	A	`conf`	Enchanced multi-threshold (MTCMOS) circuits using variable well bias. ISLPED Stephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown
2001	C	`conf`	Interconnect-centric Array Architectures for Minimum SRAM Access Time. ICCD Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl
2001	A	`conf`	Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
1998	Misc	`conf`	Designing a Testable System on a Chip. VTS Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz
1995	Misc	`conf`	A continuous density neural tree network word spotting system. ICASSP Stephen V. Kosonocky, Richard J. Mammone