Stephen Nease

14 papers C 2Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2016 J jnl
A Programmable and Configurable Mixed-Mode FPAA SoC.
IEEE Trans. Very Large Scale Integr. Syst.
Suma George, Sihwan Kim, Sahil Shah, Jennifer Hasler, Michelle Collins, Farhan Adil, Richard B. Wunderlich, Stephen Nease, Shubha Ramakrishnan
2016 C conf
Floating-gate-based intrinsic plasticity with low-voltage rate control.
ISCAS
Stephen Nease, Elisabetta Chicca
2016 J jnl
Learning in Silicon Beyond STDP: A Neuromorphic Implementation of Multi-Factor Synaptic Plasticity With Calcium-Based Dynamics.
IEEE Trans. Circuits Syst. I Regul. Pap.
Frank L. Maldonado Huayaney, Stephen Nease, Elisabetta Chicca
2016 C conf
SoC FPAA IC, PCB, and tool demonstration.
ISCAS
Sihwan Kim, Farhan Adil, Scott Koziol, Stephen Nease, Michelle Collins, Sahil Shah, Matt Kagle, Jennifer Hasler
2016 — conf
Transforming mixed-signal circuits class through SoC FPAA IC, PCB, and toolset.
EWME
Jennifer Hasler, Sihwan Kim, Sahil Shah, Farhan Adil, Michelle Collins, Scott Koziol, Stephen Nease
2015 — conf
Device mismatch in a neuromorphic system implements random features for regression.
BioCAS
Ole Richter, René Felix Reinhart, Stephen Nease, Jochen J. Steil, Elisabetta Chicca
2015 — —
Neural and analog computation on reconfigurable mixed-signal platforms.
Stephen Nease
2015 — conf
Power-efficient estimation of silicon neuron firing rates with floating-gate transistors.
ECCTD
Stephen Nease, Elisabetta Chicca
2013 J jnl
A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena.
IEEE Trans. Biomed. Circuits Syst.
Stephen Brink, Stephen Nease, Paul E. Hasler, Shubha Ramakrishnan, Richard B. Wunderlich, Arindam Basu, Brian P. Degnan
2013 J jnl
Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit.
Neural Networks
Stephen Brink, Stephen Nease, Paul E. Hasler
2013 — conf
STDP-enabled learning on a reconfigurable neuromorphic platform.
ECCTD
Stephen Nease, Stephen Brink, Paul E. Hasler
2012 J jnl
A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing.
IEEE J. Solid State Circuits
Craig Schlottmann, Samuel A. Shapero, Stephen Nease, Paul E. Hasler
2012 — conf
A mixed-mode FPAA SoC for analog-enhanced signal processing.
CICC
Craig Schlottmann, Stephen Nease, Samuel A. Shapero, Paul E. Hasler
2012 J jnl
Modeling and Implementation of Voltage-Mode CMOS Dendrites on a Reconfigurable Analog Platform.
IEEE Trans. Biomed. Circuits Syst.
Stephen Nease, Suma George, Paul E. Hasler, Scott Koziol, Stephen Brink