Stephen M. Plaza

14 papers A 1Journal 9Unranked 3
YearRankTypeTitle / Venue / Authors
2022 J jnl
neuPrint: An open access tool for EM connectomics.
Frontiers Neuroinformatics
Stephen M. Plaza, Jody Clements, Tom Dolafi, Lowell A. Umayam, Nicole N. Neubarth, Louis K. Scheffer, Stuart E. Berg
2020 J jnl
Latent Feature Representation via Unsupervised Learning for Pattern Discovery in Massive Electron Microscopy Image Volumes.
CoRR
Gary B. Huang, Huei-Fang Yang, Shin-ya Takemura, Patricia K. Rivlin, Stephen M. Plaza
2016 — conf
Focused Proofreading to Reconstruct Neural Connectomes from EM Images at Scale.
LABELS/DLMIA@MICCAI
Stephen M. Plaza
2016 J jnl
Fully-Automatic Synapse Prediction and Validation on a Large Data Set.
CoRR
Gary B. Huang, Louis K. Scheffer, Stephen M. Plaza
2016 J jnl
Large-Scale Electron Microscopy Image Segmentation in Spark.
CoRR
Stephen M. Plaza, Stuart E. Berg
2015 J jnl
Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Stephen M. Plaza, Igor L. Markov
2014 J jnl
Annotating Synapses in Large EM Datasets.
CoRR
Stephen M. Plaza, Toufiq Parag, Gary B. Huang, Donald J. Olbris, Mathew A. Saunders, Patricia K. Rivlin
2014 J jnl
Automatic Neuron Type Identification by Neurite Localization in the Drosophila Medulla.
CoRR
Ting Zhao, Stephen M. Plaza
2014 J jnl
Focused Proofreading: Efficiently Extracting Connectomes from Segmented EM Images.
CoRR
Stephen M. Plaza
2014 J jnl
Graph-based active learning of agglomeration (GALA): a Python library to segment 2D and 3D neuroimages.
Frontiers Neuroinformatics
Juan Nunez-Iglesias, Ryan Kennedy, Stephen M. Plaza, Anirban Chakraborty, William T. Katz
2014 A conf
Protecting integrated circuits from piracy with test-aware logic locking.
ICCAD
Stephen M. Plaza, Igor L. Markov
2014 — conf
Small Sample Learning of Superpixel Classifiers for EM Segmentation.
MICCAI (1)
Toufiq Parag, Stephen M. Plaza, Louis Scheffer
2011 — conf
Multi-mode redundancy removal.
ISQED
Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho
2008 — —
Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability.
Stephen M. Plaza