Stephen H. Lewis

56 papers C 2Journal 46Unranked 8
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Christopher K. Su, Paul J. Hurst, Stephen H. Lewis
2020 J jnl
A Two-Step ADC With Statistical Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi-Long Yu, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2019 J jnl
Digital Background Calibration of a Split Current-Steering DAC.
IEEE Trans. Circuits Syst. I Regul. Pap.
David J. Stoops, Jenny Kuo, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2016 C conf
An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply.
ISCAS
Mo M. Zhang, Paul J. Hurst, Stephen H. Lewis
2016 J jnl
Iterative Gain Enhancement in an Algorithmic ADC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Timothy A. Monk, Paul J. Hurst, Stephen H. Lewis
2015 J jnl
An Integrator-Based Pipelined ADC With Digital Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Dong Wang, John P. Keane, Paul J. Hurst, Stephen H. Lewis
2014 J jnl
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors.
IEEE J. Solid State Circuits
Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2013 J jnl
Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling.
IEEE J. Solid State Circuits
Omar A. Hafiz, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
2012 J jnl
A Pipelined ADC With Metastability Error Rate <10
IEEE J. Solid State Circuits
Shankar Guhados, Paul J. Hurst, Stephen H. Lewis
2012 — conf
Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors.
CICC
Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2011 J jnl
A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR.
IEEE J. Solid State Circuits
Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis
2010 J jnl
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors.
IEEE J. Solid State Circuits
Chi Ho Law, Paul J. Hurst, Stephen H. Lewis
2010 — conf
A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR.
ESSCIRC
Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis
2010 C conf
Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver.
ISCAS
Mo M. Zhang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2010 — conf
Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks.
SoCC
Oliver E. Gysel, Paul J. Hurst, Stephen H. Lewis
2010 J jnl
Prediction of the Spectrum of a Digital Delta-Sigma Modulator Followed by a Polynomial Nonlinearity.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kaveh Hosseini, Michael Peter Kennedy, Stephen H. Lewis, Bernard C. Levy
2009 J jnl
A Level-Crossing Analog-to-Digital Converter With Triangular Dither.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tunde Wang, Dong Wang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2009 — conf
An energy-aware multiple-input power supply with charge recovery for energy harvesting applications.
ISSCC
Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst, Stephen H. Lewis
2009 J jnl
Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tsung-Heng Tsai, Paul J. Hurst, Stephen H. Lewis
2009 J jnl
Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver.
IEEE Trans. Circuits Syst. II Express Briefs
Mo M. Zhang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2009 J jnl
Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA.
IEEE J. Solid State Circuits
Haoyue Wang, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
2009 J jnl
Self-Biased Unity-Gain Buffers With Low Gain Error.
IEEE Trans. Circuits Syst. II Express Briefs
Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan
2007 J jnl
A 1.4 V Supply CMOS Fractional Bandgap Reference.
IEEE J. Solid State Circuits
Raymond T. Perry, Stephen H. Lewis, A. Paul Brokaw, T. R. Viswanathan
2007 J jnl
A Passive Switched-Capacitor Finite-Impulse-Response Equalizer.
IEEE J. Solid State Circuits
Nathaniel J. Guilar, Frank Lau, Paul J. Hurst, Stephen H. Lewis
2006 — conf
A Unity-Gain Buffer with Reduced Offset and Gain Error.
CICC
Guangmao Xing, Stephen H. Lewis, T. R. Viswanathan
2006 J jnl
Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. II Express Briefs
Tsung-Heng Tsai, Paul J. Hurst, Stephen H. Lewis
2006 J jnl
Digital background calibration for memory effects in pipelined analog-to-digital converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
John P. Keane, Paul J. Hurst, Stephen H. Lewis
2005 J jnl
A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration.
IEEE J. Solid State Circuits
Carl R. Grace, Paul J. Hurst, Stephen H. Lewis
2005 — conf
A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology.
CICC
Nathaniel J. Guilar, Pak-Kim Lau, Paul J. Hurst, Stephen H. Lewis
2005 J jnl
Background interstage gain calibration technique for pipelined ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
John P. Keane, Paul J. Hurst, Stephen H. Lewis
2005 — conf
Convergence analysis of a background interstage gain calibration technique for pipelined ADCs.
ISCAS (4)
Dong Wang, John P. Keane, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
2005 J jnl
Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter".
IEEE Trans. Circuits Syst. I Regul. Pap.
Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis
2004 J jnl
A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration.
IEEE J. Solid State Circuits
Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
2004 J jnl
Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis
2004 J jnl
Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Paul J. Hurst, Stephen H. Lewis, John P. Keane, Farbod Aram, Kenneth C. Dyer
2003 — conf
A 12-bit 20-MS/s pipelined ADC with nested digital background calibration.
CICC
Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
2003 J jnl
Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue.
IEEE J. Solid State Circuits
Eric B. Blecker, Thomas M. McDonald, Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis
2002 J jnl
A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration.
IEEE J. Solid State Circuits
Shafiq M. Jamal, Daihong Fu, Nick C.-J. Chang, Paul J. Hurst, Stephen H. Lewis
2002 J jnl
A CMOS bandgap reference without resistors.
IEEE J. Solid State Circuits
Arne E. Buck, Charles L. McDonald, Stephen H. Lewis, T. R. Viswanathan
2001 J jnl
An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration.
IEEE J. Solid State Circuits
Jun Ming, Stephen H. Lewis
2001 J jnl
Editorial.
IEEE J. Solid State Circuits
Stephen H. Lewis
2001 J jnl
New associate editor.
IEEE J. Solid State Circuits
Stephen H. Lewis
2000 J jnl
New associate editor [Editor].
IEEE J. Solid State Circuits
Stephen H. Lewis
1999 J jnl
A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD.
IEEE J. Solid State Circuits
Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis
1998 J jnl
A digital background calibration technique for time-interleaved analog-to-digital converters.
IEEE J. Solid State Circuits
Daihong Fu, Kenneth C. Dyer, Stephen H. Lewis, Paul J. Hurst
1998 J jnl
An analog background calibration technique for time-interleaved analog-to-digital converters.
IEEE J. Solid State Circuits
Kenneth C. Dyer, Daihong Fu, Stephen H. Lewis, Paul J. Hurst
1997 J jnl
A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers.
IEEE J. Solid State Circuits
Krishnaswamy Nagaraj, H. Scott Fetterman, Joseph Anidjar, Stephen H. Lewis, Robert G. Renninger
1997 J jnl
A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection.
IEEE J. Solid State Circuits
Tanchu Shih, Lawrence Der, Stephen H. Lewis, Paul J. Hurst
1997 J jnl
A mixed-signal RAM decision-feedback equalizer for disk drives.
IEEE J. Solid State Circuits
Bret C. Rothenberg, James E. C. Brown, Paul J. Hurst, Stephen H. Lewis
1997 J jnl
A second-order double-sampled delta-sigma modulator using individual-level averaging.
IEEE J. Solid State Circuits
Chuc K. Thanh, Stephen H. Lewis, Paul J. Hurst
1996 J jnl
A second-order double-sampled delta-sigma modulator using additive-error switching.
IEEE J. Solid State Circuits
Ted Vinko Burmas, Kenneth C. Dyer, Paul J. Hurst, Stephen H. Lewis
1995 J jnl
A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure.
IEEE J. Solid State Circuits
Bret C. Rothenberg, Stephen H. Lewis, Paul J. Hurst
1995 J jnl
A CMOS continuous-time NTSC-to-color-difference decoder.
IEEE J. Solid State Circuits
James F. Parker, K. Wayne Current, Stephen H. Lewis
1995 J jnl
A median peak detecting analog signal processor for hard disk drive servo.
IEEE J. Solid State Circuits
Krhishnaswamy Nagaraj, Stephen H. Lewis, Robert W. Walden, Glen E. Offord, Reza S. Shariatdoust, Jyoti A. Sabnis, Robert O. Peruzzi, Jeffrey R. Barner, Joseph Plany, Robert P. Mento, Vafa A. Rakshani, Richard W. Hull
1995 J jnl
An 80-Msample/s video switched-capacitor filter using a parallel biquadratic structure.
IEEE J. Solid State Circuits
Steven K. Berg, Paul J. Hurst, Stephen H. Lewis
1992 J jnl
A 10-b 20-Msample/s analog-to-digital converter.
IEEE J. Solid State Circuits
Stephen H. Lewis, H. Scott Fetterman, George F. Gross, Ravi Ramachandran, T. R. Viswanathan