Stephen Dean Brown

50 papers A* 5A 12B 8C 1Misc 1Journal 11Unranked 12

Year	Rank	Type	Title / Venue / Authors
2018	—	`conf`	Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems. HEART Bain Syrowik, Blair Fort, Stephen Dean Brown
2017	J	`jnl`	From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson
2014	B	`conf`	Modulo SDC scheduling with recurrence minimization in high-level synthesis. FPL Andrew Canis, Stephen Dean Brown, Jason Helge Anderson
2014	B	`conf`	Source-level debugging for FPGA high-level synthesis. FPL Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson
2013	A	`conf`	High-level synthesis with LegUp: a crash course for users and researchers. FPGA Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi
2013	J	`jnl`	LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson
2013	A	`conf`	Multi-pumping for resource reduction in FPGA high-level synthesis. DATE Andrew Canis, Jason Helge Anderson, Stephen Dean Brown
2011	J	`jnl`	Toward Automated ECOs in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu
2010	J	`jnl`	Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tomasz S. Czajkowski, Stephen Dean Brown
2009	A	`conf`	Towards automated ECOs in FPGAs. FPGA Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour
2008	—	`conf`	Delay driven AIG restructuring using slack budget management. ACM Great Lakes Symposium on VLSI Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
2008	B	`conf`	Fast toggle rate computation for FPGA circuits. FPL Tomasz S. Czajkowski, Stephen Dean Brown
2008	J	`jnl`	Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tomasz S. Czajkowski, Stephen Dean Brown
2008	A*	`conf`	Functionally linear decomposition and synthesis of logic circuits for FPGAs. DAC Tomasz S. Czajkowski, Stephen Dean Brown
2008	J	`jnl`	Scalable Synthesis and Clustering Techniques Using Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
2007	J	`jnl`	An area-efficient timing closure technique for FPGAs using Shannon's expansion. Integr. Deshanand P. Singh, Stephen Dean Brown
2007	—	`conf`	BddCut: Towards Scalable Symbolic Cut Enumeration. ASP-DAC Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
2007	J	`jnl`	FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2007	C	`conf`	Incremental placement for structured ASICs using the transportation problem. VLSI-SoC Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2007	J	`jnl`	Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
2007	A*	`conf`	Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. DAC Tomasz S. Czajkowski, Stephen Dean Brown
2006	Misc	`conf`	A Multithreaded Soft Processor for SoPC Area Reduction. FCCM Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown
2006	B	`conf`	Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
2006	—	`conf`	Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
2006	J	`jnl`	Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
2006	A	`conf`	Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2006	B	`conf`	Modular Partitioning for Incremental Compilation. FPL Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry P. Borer
2005	A	`conf`	Experiences with Soft-Core Processor Design. IPDPS Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown
2005	A	`conf`	FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005	B	`conf`	FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005	A*	`conf`	FPGA technology mapping: a study of optimality. DAC Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown
2005	A*	`conf`	Incremental retiming for FPGA physical synthesis. DAC Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2005	B	`conf`	Post-Placement BDD-Based Decomposition for FPGAs. FPL Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
2005	—	`conf`	Two-stage physical synthesis for FPGAs. CICC Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
2004	—	`conf`	Retiming aware clustering for sequential circuits. FPT Mehrdad Eslami Dehkordi, Stephen Dean Brown
2004	—	`conf`	The Quartus University Interface Program: enabling advanced FPGA research. FPT Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown
2003	—	`conf`	An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI Deshanand P. Singh, Stephen Dean Brown
2003	—	`conf`	Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown
2003	—	`conf`	Performance-driven recursive multi-level clustering. FPT Mehrdad Eslami Dehkordi, Stephen Dean Brown
2003	A	`conf`	Recursive circuit clustering for minimum delay and area. FPGA Mehrdad Eslami Dehkordi, Stephen Dean Brown
2002	B	`conf`	Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic
2002	A	`conf`	Constrained clock shifting for field programmable gate arrays. FPGA Deshanand P. Singh, Stephen Dean Brown
2002	A	`conf`	Incremental placement for layout driven optimizations on FPGAs. ICCAD Deshanand P. Singh, Stephen Dean Brown
2002	A	`conf`	Integrated retiming and placement for field programmable gate arrays. FPGA Deshanand P. Singh, Stephen Dean Brown
2002	—	`conf`	The effect of cluster packing and node duplication control in delay driven clustering. FPT Mehrdad Eslami Dehkordi, Stephen Dean Brown
2001	A	`conf`	The case for registered routing switches in field programmable gate arrays. FPGA Deshanand P. Singh, Stephen Dean Brown
1998	A	`conf`	An LPGA with Foldable PLA-style Logic Blocks. FPGA Jason Helge Anderson, Stephen Dean Brown
1998	A*	`conf`	Technology Mapping for Large Complex PLDs. DAC Jason Helge Anderson, Stephen Dean Brown
1997	—	`conf`	On two-step routing for FPGAS. ISPD Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic
1993	J	`jnl`	A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic