Stephen Brown

41 papers A* 2A 6B 4C 3Misc 4Journal 10Unranked 11
YearRankTypeTitle / Venue / Authors
2021 B conf
Leveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures.
FPL
Linqiao Liu, Stephen Brown
2020 A conf
Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator.
FPGA
Tanner Young-Schultz, Lothar Lilge, Stephen Brown, Vaughn Betz
2017 B conf
FISH: Linux system calls for FPGA accelerators.
FPL
Kevin Nam, Blair Fort, Stephen Brown
2016 J jnl
A Survey and Evaluation of FPGA High-Level Synthesis Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels
2016 — conf
A unified software approach to specify pipeline and spatial parallelism in FPGA hardware.
ASAP
Jongsok Choi, Ruolong Lian, Stephen Brown, Jason Helge Anderson
2016 — ch.
LegUp High-Level Synthesis.
FPGAs for Software Programmers
Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Brown, Jason Helge Anderson
2015 — conf
Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware.
FPT
Jongsok Choi, Stephen Brown, Jason Helge Anderson
2015 J jnl
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware.
ACM Trans. Reconfigurable Technol. Syst.
Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Brown, Jason Helge Anderson
2014 C conf
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis.
EUC
Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson
2013 J jnl
Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2013 — conf
From C to Blokus Duo with LegUp high-level synthesis.
FPT
Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Brown, Jason Helge Anderson
2013 — conf
From software threads to parallel hardware in high-level synthesis for FPGAs.
FPT
Jongsok Choi, Stephen Brown, Jason Helge Anderson
2013 Misc conf
From software to accelerators with LegUp high-level synthesis.
CASES
Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson
2013 Misc conf
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs.
FCCM
Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Brown, Jason Helge Anderson
2012 Misc conf
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems.
FCCM
Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski
2012 A conf
Impact of FPGA architecture on resource sharing in high-level synthesis.
FPGA
Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Brown, Tomasz S. Czajkowski
2011 A conf
LegUp: high-level synthesis for FPGA-based processor/accelerator systems.
FPGA
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski
2011 — conf
Low-cost hardware profiling of run-time and energy in FPGA embedded processors.
ASAP
Mark Aldham, Jason Helge Anderson, Stephen Brown, Andrew Canis
2010 — conf
Recent FPGA Advances and Challenges.
ERSA
Vaughn Betz, Stephen Brown
2010 — conf
Technology issues facing the world's largest integrated circuits.
FPT
Stephen Brown
2009 B conf
Enhancements to FPGA design methodology using streaming.
FPL
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2008 — conf
Stream Programming for FPGAs.
FDL (Selected Papers)
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2008 C conf
Towards Compilation of Streaming Programs into FPGA Hardware.
FDL
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2007 — conf
Leveraging FPGA Technology for Digital Logic and Embedded Systems Education.
MSE
Stephen Brown
2007 — conf
On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees.
ICSOFT (PL/DPS/KE/MUSE)
Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2003 Misc conf
Use of HDLs in teaching of computer hardware courses.
WCAE
Zvonko G. Vranesic, Stephen Brown
2000 A conf
Technology mapping issues for an FPGA with lookup tables and PLA-like blocks.
FPGA
Alireza Kaviani, Stephen Brown
2000 B conf
The NUMAchine Multiprocessor.
ICPP
R. Grindley, Tarek S. Abdelrahman, Stephen Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
1999 J jnl
The Hybrid Field-Programmable Architecture.
IEEE Des. Test Comput.
Alireza Kaviani, Stephen Brown
1998 — conf
Computational field programmable architecture.
CICC
Alireza Kaviani, Daniel Vranesic, Stephen Brown
1998 A* conf
Design and Implementation of the NUMAchine Multiprocessor.
DAC
A. Grbic, Stephen Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
1996 A* conf
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools.
DAC
Stephen Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic
1996 J jnl
FPGA Architectural Research: A Survey.
IEEE Des. Test Comput.
Stephen Brown
1996 J jnl
FPGA and CPLD Architectures: A Tutorial.
IEEE Des. Test Comput.
Stephen Brown, Jonathan Rose
1996 A conf
Hybrid FPGA Architecture.
FPGA
Alireza Kaviani, Stephen Brown
1996 J jnl
Minimizing FPGA Interconnect Delays.
IEEE Des. Test Comput.
Stephen Brown, Muhammad M. Khellah, Zvonko G. Vranesic
1996 J jnl
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays.
VLSI Design
Stephen Brown, Muhammad M. Khellah, Guy Lemieux
1992 J jnl
A detailed router for field-programmable gate arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Stephen Brown, Jonathan Rose, Zvonko G. Vranesic
1992 C conf
Improving FPGA Routing Architectures Using Architecture and CAD Interactions.
ICCD
Benjamin Tseng, Jonathan Rose, Stephen Brown
1991 J jnl
Flexibility of interconnection structures for field-programmable gate arrays.
IEEE J. Solid State Circuits
Jonathan Rose, Stephen Brown
1990 A conf
A Detailed Router for Field-Programmable Gate Arrays.
ICCAD
Stephen Brown, Jonathan Rose, Zvonko G. Vranesic