Stephen A. Szygenda

55 papers A* 14B 1C 3Misc 3Journal 14Unranked 19

Year	Rank	Type	Title / Venue / Authors
2014	—	`conf`	System Probability Distribution Modeling Using MDDs. ISMVL Mitchell A. Thornton, Theodore W. Manikas, Stephen A. Szygenda, Shinobu Nagayama
2008	J	`jnl`	A Systems Engineering Approach for Identifying the Most Critical Links of a Highway System: A Framework Consisting of a Methodology and Mathematical Model. IEEE Syst. J. Gerard Ibarra, Jerrell T. Stracener, Stephen A. Szygenda
2008	J	`jnl`	Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility. Int. J. Bus. Inf. Syst. Chad M. Lawler, Michael A. Harper, Stephen A. Szygenda, Mitchell A. Thornton
2004	—	`conf`	A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking. ISVLSI Lun Li, Mitchell A. Thornton, Stephen A. Szygenda
2004	—	`conf`	Test vector generation and classification using FSM traversals. ISCAS (5) Ralph Marczynski, Mitchell A. Thornton, Stephen A. Szygenda
2003	J	`jnl`	Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem. Simul. Sungho Kang, Stephen A. Szygenda
1997	—	`conf`	Concurrent Fault and Design Error Simulation in Interactive Simulation Automation System. Annual Simulation Symposium Youngmin Hur, Saghir A. Shaikh, Silvian Goldenberg, Dominik Kacprzak, Stephen A. Szygenda
1997	—	`conf`	Exploiting Component/Event-Level Parallelism in Concurrent Fault and Design Error Simulation. Annual Simulation Symposium Saghir A. Shaikh, Stephen A. Szygenda
1997	B	`conf`	Multiresolution BSP Trees Applied to Terrain, Transparency, and General Objects. Graphics Interface Charles Wiley, A. T. Campbell III, Stephen A. Szygenda, Donald S. Fussell, Fred Hudson
1996	—	`conf`	A Graphical Simulation and Automatic Model Generation System. ESM Youngmin Hur, Stephen A. Szygenda
1996	J	`jnl`	A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture. VLSI Design Sungho Kang, Youngmin Hur, Stephen A. Szygenda
1996	—	`conf`	A Simulation Tool for Design Error Models Utilizing Error Compression and Sampling. Annual Simulation Symposium Youngmin Hur, Stephen A. Szygenda
1996	J	`jnl`	An Integrated Hardware Array for Very High Speed Logic Simulation. VLSI Design E. Scott Fehr, Stephen A. Szygenda, Granville E. Ott
1996	Misc	`conf`	CON PDPTA Saghir A. Shaikh, Silvian Goldenberg, Stephen A. Szygenda
1995	A*	`conf`	Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. HPCA Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang
1995	—	`conf`	Special purpose array processor for digital logic simulation. Annual Simulation Symposium Youngmin Hur, Stephen A. Szygenda
1995	C	`conf`	Statistics on concurrent fault and design error simulation. ICCD Brian Grayson, Saghir A. Shaikh, Stephen A. Szygenda
1994	J	`jnl`	Automatic Functional Model Generation for Parallel Fault and Design Error Simulations. Int. J. Artif. Intell. Tools Shuchih Ernest Chang, Stephen A. Szygenda
1994	J	`jnl`	Automatic Simulator Generation System. Simul. Sungho Kang, Stephen A. Szygenda
1994	J	`jnl`	Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling. IEEE Des. Test Comput. Sungho Kang, Stephen A. Szygenda
1994	J	`jnl`	The simulation automation system (SAS); concepts, implementation, and results. IEEE Trans. Very Large Scale Integr. Syst. Sungho Kang, Stephen A. Szygenda
1993	—	`conf`	Automatic VHDL Model Generation System. CHDL Sungho Kang, Stephen A. Szygenda
1993	C	`conf`	m3D: A Multidimensional Dynamic Configurable Router. ISCAS Charles Wiley, K. M. Lau, Stephen A. Szygenda
1992	C	`conf`	Modeling and Simulation of Design Errors. ICCD Sungho Kang, Stephen A. Szygenda
1992	—	`conf`	New design error modeling and metrics for design validation. EURO-DAC Sungho Kang, Stephen A. Szygenda
1992	—	`conf`	The automatic element routine generator: an automatic programming tool for functional simulator design. Annual Simulation Symposium Cheng-I Chuang, Stephen A. Szygenda, James D. Baker
1990	J	`jnl`	MixMOS: a mixed-level simulator for digital MOS circuits using a new algebraic approach. Comput. Aided Des. Jin-Hyeung Kong, Stephen A. Szygenda
1988	—	`conf`	SMARTGEN: The Implementation of an Expert System for the Generation of Digital Logic Diagnostic Tests. IEA/AIE (Vol. 1) Asad Karim, Stephen A. Szygenda
1987	—	`ed.`	Proceedings of the 1987 Fall Joint Computer Conference on Exploring technology: today and tomorrow FJCC Stephen A. Szygenda
1987	—	`conf`	Technology transfer: commercializing university research. FJCC Stephen A. Szygenda, M. Wilson
1982	A*	`ed.`	9th International Symposium on Computer Architecture (ISCA 1982), Austin, TX, USA, April 26-29, 1982 ISCA Stephen A. Szygenda, John Hughes, Matt Blanton, Terry J. Wagner, Dennis J. Frailey, Tom Gunter, Chuck McLeavy, G. Jack Lipovski, Miroslaw Malek
1978	A*	`ed.`	Proceedings of the 15th Design Automation Conference, DAC '78, Las Vegas, Nevada, USA, June 19-21, 1978 DAC Stephen A. Szygenda
1977	—	`conf`	Design of a diagnosable and fault-tolerant input/output controller. AFIPS National Computer Conference Ajoy K. Bose, Stephen A. Szygenda
1977	A*	`conf`	Detection of static and dynamic hazards in logic nets. DAC Ajoy K. Bose, Stephen A. Szygenda
1977	A*	`ed.`	Proceedings of the 14th Design Automation Conference, DAC '77, New Orleans, Louisiana, USA, June 20-22, 1977 DAC Judith G. Brinsfield, Stephen A. Szygenda, David W. Hightower
1976	A*	`conf`	A Data Structure and Drive Mechanism for a Table-Driven Simulation System Employing Multilevel Structural Representations of Digital Systems. ICSE N. Billawala, Stephen A. Szygenda, Ewald W. Thomson
1976	J	`jnl`	Modeling and Digital Simulation for Design Verification and Diagnosis. IEEE Trans. Computers Stephen A. Szygenda, Edward W. Thompson
1976	A*	`ed.`	Proceedings of the 13th Design Automation Conference, DAC '76, San Francisco, California, USA, June 28-30, 1976 DAC Donald J. Humcke, J. Michael Galey, Stephen A. Szygenda, Pat O. Pistilli, Nitta P. Dooner, Judith G. Brinsfield, J. S. Olila
1975	J	`jnl`	Digital Logic Simulation in a Time-Based, Table-Driven Environment. Computer Stephen A. Szygenda, Edward W. Thompson
1975	J	`jnl`	Digital Logic Simulation in a Time-Based, Table-Driven Environment. Computer Edward W. Thompson, Stephen A. Szygenda
1975	J	`jnl`	Digital Systems Simulation. Computer Stephen A. Szygenda
1975	A*	`ed.`	Proceedings of the 12th Design Automation Conference, DAC '75, Boston, Massachusetts, USA, June 23-25, 1975 DAC Robert B. Hitchcock Sr., Donald J. Humcke, Stephen A. Szygenda
1975	A*	`conf`	Three levels of accuracy for the simulation of different fault types in digital systems. DAC Edward W. Thompson, Stephen A. Szygenda
1974	Misc	`conf`	Implemented techniques for handling spikes in an assignable delay simulator. WSC Stephen A. Szygenda, Anthony A. Lekkos, John L. Fike
1974	A*	`conf`	Timing analysis for digital fault simulation using assignable delays. DAC Edward W. Thompson, Stephen A. Szygenda, N. Billawala, R. Pierce
1973	A*	`conf`	Deriving Design Guidelines for Diagnosable Computer Systems. ISCA John M. Hemphill, Stephen A. Szygenda
1973	A*	`conf`	Integrated techniques for functional and gate-level digital logic simulation. DAC Stephen A. Szygenda, Anthony A. Lekkos
1973	A*	`ed.`	Proceedings of the 1st Annual Symposium on Computer Architecture, Gainesville, FL, USA, December 1973 ISCA G. Jack Lipovski, Stephen A. Szygenda
1973	—	`conf`	Techniques and modules for element specification in a time - delay logic simulator. ANSS John L. Fike, Stephen A. Szygenda
1972	—	`conf`	Fault insertion techniques and models for digital logic simulation. AFIPS Fall Joint Computing Conference (2) Stephen A. Szygenda, Edward W. Thompson
1972	—	`conf`	Modular requirements for digital logic simulation at a predefined functional level. ACM Annual Conference (1) Cliff W. Hemming Jr., Stephen A. Szygenda
1972	A*	`conf`	TEGAS2 - anatomy of a general purpose TEST GENERATION AND SIMULATION system for digital logic. DAC Stephen A. Szygenda
1971	—	`conf`	Coding techniques for failure recovery in a distributive modular memory organization. AFIPS Spring Joint Computing Conference Stephen A. Szygenda, Michael J. Flynn
1971	Misc	`conf`	Time flow mechanisms for use in digital logic simulation. WSC Stephen A. Szygenda, Cliff W. Hemming Jr., John M. Hemphill
1970	—	`conf`	A model and implementation of a universal time delay simulator for large digital nets. AFIPS Spring Joint Computing Conference Stephen A. Szygenda, David M. Rouse, Edward W. Thompson