Stephane Bronckers

11 papers A 2Journal 6Unranked 3

Year	Rank	Type	Title / Venue / Authors
2011	J	`jnl`	Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. IEEE J. Solid State Circuits Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal
2010	—	`conf`	Design issues and considerations for low-cost 3D TSV IC technology. ISSCC Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne
2010	J	`jnl`	Substrate Noise Coupling Mechanisms in Lightly Doped CMOS Transistors. IEEE Trans. Instrum. Meas. Stephane Bronckers, Geert Van der Plas, Gerd Vandersteen, Yves Rolain
2009	J	`jnl`	A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephane Bronckers, Karen Scheir, Geert Van der Plas, Gerd Vandersteen, Yves Rolain
2009	J	`jnl`	Experimental Analysis of the Coupling Mechanisms Between a 4 GHz PPA and a 5-7 GHz LC -VCO. IEEE Trans. Instrum. Meas. Stephane Bronckers, Gerd Vandersteen, Ludwig De Locht, Michael Libois, Geert Van der Plas, Yves Rolain
2008	J	`jnl`	A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS. IEEE J. Solid State Circuits Karen Scheir, Stephane Bronckers, Jonathan Borremans, Piet Wambacq, Yves Rolain
2008	—	`conf`	A 52GHz Phased-Array Receiver Front-End in 90nm Digital CMOS. ISSCC Karen Scheir, Stephane Bronckers, Jonathan Borremans, Piet Wambacq, Yves Rolain
2008	J	`jnl`	A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. IEEE J. Solid State Circuits Jonathan Borremans, Andrea Bevilacqua, Stephane Bronckers, Morin Dehan, Maarten Kuijk, Piet Wambacq, Jan Craninckx
2008	—	`conf`	A Single-Inductor Dual-Band VCO in a 0.06mm ISSCC Jonathan Borremans, Stephane Bronckers, Piet Wambacq, Maarten Kuijk, Jan Craninckx
2007	A	`conf`	Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. DATE Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain
2006	A	`conf`	Systematic stability-analysis method for analog circuits. DATE Gerd Vandersteen, Stephane Bronckers, Petr Dobrovolný, Yves Rolain