Stephan Henzler

20 papers A 2C 1Journal 5Unranked 12
YearRankTypeTitle / Venue / Authors
2016 — conf
A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC.
APCCAS
Junjie Kong, Stephan Henzler, Doris Schmitt-Landsiedel, Liter Siek
2010 A conf
Digitalization of mixed-signal functionality in nanometer technologies.
ICCAD
Stephan Henzler
2009 — conf
Adaptive circuit block model for power supply noise analysis of low power system-on-chip.
SoC
Matthias Eireiner, Doris Schmitt-Landsiedel, Paul Wallner, Andreas Schöne, Stephan Henzler, Ulrich Fiedler
2008 — conf
90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization.
ISSCC
Stephan Henzler, Siegmar Koeppe, Winfried Kamp, Hans Mulatz, Doris Schmitt-Landsiedel
2008 J jnl
A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion.
IEEE J. Solid State Circuits
Stephan Henzler, Siegmar Koeppe, Dominik Lorenz, Winfried Kamp, Ronald Kuenemund, Doris Schmitt-Landsiedel
2008 J jnl
Design and Application of Power Optimized High-Speed CMOS Frequency Dividers.
IEEE Trans. Very Large Scale Integr. Syst.
Stephan Henzler, Siegmar Koeppe
2007 J jnl
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions.
IEEE J. Solid State Circuits
Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Andre Bonnardot, Steffen Buch, Matthias Sauer
2007 J jnl
In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations.
IEEE J. Solid State Circuits
Matthias Eireiner, Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2007 — conf
Variation tolerant high resolution and low latency time-to-digital converter.
ESSCIRC
Stephan Henzler, Siegmar Koeppe, Dominik Lorenz, Winfried Kamp, Ronald Kuenemund, Doris Schmitt-Landsiedel
2006 — conf
A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions.
ISSCC
Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Hamid Mabrouki, Goulhamid Juhoor, Matthias Sauer
2006 J jnl
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead.
IEEE J. Solid State Circuits
Stephan Henzler, Georg Georgakos, Matthias Eireiner, Thomas Nirschl, Christian Pacha, Jörg Berthold, Doris Schmitt-Landsiedel
2006 A conf
High-speed low-power frequency divider with intrinsic phase rotator.
ISLPED
Stephan Henzler, Siegmar Koeppe
2005 — conf
Dynamic state-retention flip flop for fine-grained sleep-transistor scheme.
ESSCIRC
Stephan Henzler, Thomas Nirschi, Christian Pacha, Peter Spindler, Philip Teichmann, Michael Fulde, Jürgen Fischer, Matthias Eireiner, Thomas Fischer, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2005 — conf
Impact of process parameter variations on the energy dissipation in adiabatic logic.
ECCTD
Jürgen Fischer, Ettore Amirante, Thomas Nirschl, Philip Teichmann, Stephan Henzler, Doris Schmitt-Landsiedel
2005 — conf
Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits.
Conf. Computing Frontiers
Stephan Henzler, Thomas Nirschl, Matthias Eireiner, Ettore Amirante, Doris Schmitt-Landsiedel
2005 — conf
Power-Clock Gating in Adiabatic Logic Circuits.
PATMOS
Philip Teichmann, Jürgen Fischer, Stephan Henzler, Ettore Amirante, Doris Schmitt-Landsiedel
2004 — conf
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.
PATMOS
Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2004 — conf
Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.
PATMOS
Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel
2003 C conf
Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes.
VLSI-SOC
Stephan Henzler, Markus Koban, Doris Schmitt-Landsiedel, Jörg Berthold, Georg Georgakos
2003 — conf
Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.
VLSI-SoC (Selected Papers)
Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel