Stephan Eggersglüß

59 papers A 8B 8C 6Journal 11Unranked 22

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Exploiting weak detections for optimizing pattern generation in Defect-Oriented Cell-Aware ATPG. ITC-Asia Alessandro Ciullo, Stephan Eggersglüß, Daniel Tille, Andreas Glowatz, Giusy Iaria, Paolo Bernardi
2024	A	`conf`	A Cell-aware Transistor State Stress Model and its Application for Quality Measurement. ITC Stephan Eggersglüß, Andreas Glowatz
2024	J	`jnl`	The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test Janusz Rajski, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer
2023	J	`jnl`	A New Static Compaction of Deterministic Test Sets. IEEE Trans. Very Large Scale Integr. Syst. Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
2021	A	`conf`	On Reduction of Deterministic Test Pattern Sets. ITC Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer
2019	—	`conf`	Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements. LATS Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
2019	A	`conf`	IEEE European Test Symposium (ETS). ITC Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena-Ioana Vatajelu
2019	B	`conf`	Machine Learning-based Prediction of Test Power. ETS Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
2019	—	`conf`	Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. ITC-Asia Stephan Eggersglüß
2019	A	`conf`	Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. ITC Stephan Eggersglüß
2018	—	`conf`	Approximation-aware testing for approximate circuits. ASP-DAC Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
2018	C	`conf`	Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. DDECS Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
2017	B	`conf`	Foreword. ETS Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken
2017	—	`conf`	Identification of Efficient Clustering Techniques for Test Power Activity on the Layout. ATS Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
2017	—	`conf`	Machine learning based test pattern analysis for localizing critical power activity areas. DFT Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler
2017	A	`conf`	Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. DATE Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
2017	—	`conf`	Reconfigurable TAP controllers with embedded compression for large test data volume. DFT Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
2017	—	`conf`	Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. SSCI Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler
2016	—	`conf`	Exploring superior structural materials using multi-objective optimization and formal techniques. ISED Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler
2016	—	`conf`	Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. ATS Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
2016	J	`jnl`	On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
2016	B	`conf`	SAT-based post-processing for regional capture power reduction in at-speed scan test generation. ETS Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen
2016	B	`conf`	VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. ETS Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
2015	B	`conf`	Compact test set generation for test compression-based designs. ETS Stephan Eggersglüß
2014	J	`jnl`	An effective fault ordering heuristic for SAT-based dynamic test compaction techniques. it Inf. Technol. Stephan Eggersglüß, Rolf Drechsler
2014	—	`conf`	Automated formal verification of X propagation with respect to testability issues. IDT Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß
2014	J	`jnl`	Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets. J. Electron. Test. Stephan Eggersglüß
2014	B	`conf`	Optimization-based multiple target test generation for highly compacted test sets. ETS Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
2014	—	`conf`	Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. DTIS Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
2013	A	`conf`	Improved SAT-based ATPG: more constraints, better compaction. ICCAD Stephan Eggersglüß, Robert Wille, Rolf Drechsler
2013	—	`conf`	PASSAT 2.0: A multi-functional SAT-based testing framework. LATW Rolf Drechsler, Melanie Diepenbeck, Stephan Eggersglüß, Robert Wille
2013	—	`conf`	Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill. Asian Test Symposium Stephan Eggersglüß
2012	J	`jnl`	A Highly Fault-Efficient SAT-Based ATPG Flow. IEEE Des. Test Comput. Stephan Eggersglüß, Rolf Drechsler
2012	C	`conf`	A new SAT-based ATPG for generating highly compacted test sets. DDECS Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
2012	—	`book`	High Quality Test Pattern Generation and Boolean Satisfiability. Stephan Eggersglüß, Rolf Drechsler
2012	—	`conf`	Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization. Asian Test Symposium Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
2011	A	`conf`	As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. DATE Stephan Eggersglüß, Rolf Drechsler
2011	J	`jnl`	Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Stephan Eggersglüß, Rolf Drechsler
2010	C	`conf`	Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
2010	B	`conf`	Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. ETS Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler
2010	J	`jnl`	Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
2010	J	`jnl`	MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler
2010	—	`—`	Robust algorithms for high quality test pattern generation using Boolean satisfiability. Stephan Eggersglüß
2010	—	`ch.`	Robuste Erfüllbarkeitsalgorithmen zur Generierung hochwertiger Testmuster für digitale Schaltungen. Ausgezeichnete Informatikdissertationen Stephan Eggersglüß
2009	J	`jnl`	Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
2009	B	`conf`	Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. ETS Stephan Eggersglüß, Rolf Drechsler
2009	—	`conf`	Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
2009	—	`book`	Test Pattern Generation using Boolean Proof Engines. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
2009	A	`conf`	Timing Arc based logic analysis for false noise reduction. ICCAD Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
2008	J	`jnl`	On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille
2008	—	`conf`	On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ISMVL Stephan Eggersglüß, Rolf Drechsler
2008	—	`conf`	SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
2007	C	`conf`	Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2007	—	`conf`	Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
2007	—	`conf`	Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
2007	—	`conf`	Improving Test Pattern Compactness in SAT-based ATPG. ATS Stephan Eggersglüß, Rolf Drechsler
2007	C	`conf`	SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
2007	—	`conf`	SWORD: A SAT like Prover Using Word Level Information. VLSI-SoC (Selected Papers) Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
2007	C	`conf`	SWORD: A SAT like prover using word level information. VLSI-SoC Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler