Steffen Rülke

24 papers A 4C 9Journal 1Unranked 9
YearRankTypeTitle / Venue / Authors
2012 C conf
Bounded model checking of Contiki applications.
DDECS
Thilo Vörtler, Steffen Rülke, Petra Hofstedt
2009 J jnl
Advanced verification by automatic property generation.
IET Comput. Digit. Tech.
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
2009 — conf
Automatic debugging of System-on-a-Chip designs.
SoCC
Frank Rogin, Rolf Drechsler, Steffen Rülke
2008 A conf
Automatic Generation of Complex Properties for Hardware Designs.
DATE
Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
2008 — conf
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs.
ISVLSI
Maik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke
2007 C conf
A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator.
DSD
Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt
2007 C conf
A Tailored Design Partitioning Method for Hardware Emulation.
IEEE International Workshop on Rapid System Prototyping
Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt
2007 C conf
An Integrated SystemC Debugging Environment.
FDL
Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
2007 A conf
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs.
IPDPS
Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker
2006 A conf
A high-level target-precise model for designing reconfigurable HW tasks.
IPDPS
Maik Boden, Steffen Rülke, Jürgen Becker
2006 C conf
Non-Intrusive High-level SystemC Debugging.
FDL
Frank Rogin, Erhard Fehlauer, Steffen Rülke, Sebastian Ohnewald, Thomas Berndt
2005 A conf
A Low-Cost Realization of an Adaptable Protocol Processing Unit.
IPDPS
Maik Boden, Alex Gleich, Steffen Rülke, Ulrich Nageldinger
2004 C conf
Cost-Efficient Implementation of Adaptive Finite State Machines.
DSD
Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke
2004 — conf
Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment.
PARELEC
Jörg Schneider, Vincent Kotzsch, Steffen Rülke
2004 — conf
IPQ: IP Qualification for Efficient System Design.
ISQED
Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki
2002 — conf
Eine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen.
MBMV
Jörg Schneider, Maik Boden, Steffen Rülke
2002 C conf
Enhanced Reusability for SoC-Based HW/SW Co-Design.
DSD
Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke
2002 C conf
Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis.
DSD
Ronny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig
2001 C conf
Two-Criterial Constraint-Driven FSM State Encoding for Low Power.
DSD
Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo
1998 — conf
FPGA based prototyping using a target driven FSM partitioning strategy.
ICECS
Klaus Feske, Steffen Rülke, Manfred Koegst
1998 — conf
Multi-Criterial State Assignment for Low Power FSM Design.
EUROMICRO
Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske
1998 — conf
Verringerung der Leistungsaufnahme in sequentiellen Schaltungen durch Vorlogik und zweistufige Zustandskodierung.
MBMV
Manfred Koegst, Günter Franke, Klaus Feske, Steffen Rülke
1997 — conf
Low Power Design of FSMs by State Assignment and Disabling Self-Loops.
EUROMICRO
Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske
1990 — —
EASY - ein Werkzeug zur Unterstützung der automatischen High-Level-Synthese des Datenteils digitaler Systeme: Konzeption und Implementierung einer Experimentalversion.
Steffen Rülke