Stefanos Sidiropoulos

13 papers A 1Journal 8Unranked 4

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET. VLSI Technology and Circuits Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos
2013	J	`jnl`	A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications. IEEE J. Solid State Circuits Aida Varzaghani, Athos Kasapi, Dimitri Loizos, Song-Hee Paik, Shwetabh Verma, Sotirios Zogopoulos, Stefanos Sidiropoulos
2013	—	`conf`	A 10.3GS/s 6b flash ADC for 10G Ethernet applications. ISSCC Shwetabh Verma, Athos Kasapi, Li-min Lee, Dean Liu, Dimitri Loizos, Song-Hee Paik, Aida Varzaghani, Sotirios Zogopoulos, Stefanos Sidiropoulos
2006	—	`conf`	An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS. ISSCC Shahriar Rabii, Nikhil Acharya, Pak Chau, Joseph Dao, Arnold Feldman, Haw-Jyh Liaw, Dean Liu, Marc Loinaz, Manuel Luschas, Azmeer Salleh, Siddharth Sheth, Stefanos Sidiropoulos, Donald Stark, Shwetabh Verma
2006	—	`conf`	Improving CDR Performance via Estimation. ISSCC Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz
2003	J	`jnl`	A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. IEEE J. Solid State Circuits Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos
2003	A	`conf`	A Framework for Designing Reusable Analog Circuits. ICCAD Dean Liu, Stefanos Sidiropoulos, Mark Horowitz
2000	J	`jnl`	A variable-frequency parallel I/O interface with adaptive power-supply regulation. IEEE J. Solid State Circuits Gu-Yeon Wei, Jaeha Kim, Dean Liu, Stefanos Sidiropoulos, Mark A. Horowitz
1998	J	`jnl`	High-speed electrical signaling: overview and limitations. IEEE Micro Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos
1997	J	`jnl`	A 700-Mb/s/pin CMOS signaling interface using current integrating receivers. IEEE J. Solid State Circuits Stefanos Sidiropoulos, Mark Horowitz
1997	J	`jnl`	A semidigital dual delay-locked loop. IEEE J. Solid State Circuits Stefanos Sidiropoulos, Mark A. Horowitz
1996	J	`jnl`	A speed, power, and supply noise evaluation of ECL driver circuits. IEEE J. Solid State Circuits Norman P. Jouppi, Stefanos Sidiropoulos, Suresh Menon
1991	J	`jnl`	Weighted Round-Robin Cell Multiplexing in a General-Purpose ATM Switch Chip. IEEE J. Sel. Areas Commun. Manolis Katevenis, Stefanos Sidiropoulos, Costas Courcoubetis