Stefania Perri

112 papers A 1B 4C 7Misc 1Journal 69Unranked 30

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Hardware-Aware Methodology for Distributed In-Network Intelligence on FPGA-Based SmartNICs. IEEE Netw. Lett. Fanny Spagnolo, Mattia Giovanni Spina, Stefania Perri, Antonio Iera, Pasquale Corsonello
2025	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. ACM Comput. Surv. Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke, Stefania Perri
2025	—	`conf`	Approximate Swish Activation Function for Low-Energy Yet Low-Error VLSI Implementations. ISVLSI Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
2025	J	`jnl`	C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. Fanny Spagnolo, Massimo Vatalaro, Stefania Perri, Felice Crupi, Pasquale Corsonello
2025	J	`jnl`	Design of Energy Efficient RFET-Based Polymorphic Logic Gates. IEEE Trans. Circuits Syst. II Express Briefs Fanny Spagnolo, Pasquale Corsonello, Stefania Perri
2025	J	`jnl`	HIMAM: Hardware Implementation of Multiply-and-Max/Min Layers for Energy-Efficient DNN Inference. IEEE Trans. Circuits Syst. II Express Briefs Fanny Spagnolo, Pasquale Corsonello, Stefania Perri
2025	A	`conf`	Multi-Partner Project: Architectures and Design Methodologies to Accelerate AI Workloads. The ICSC Flagship 2 Project. DATE Cristina Silvano, Fabrizio Ferrandi, Serena Curzel, Daniele Ielmini, Stefania Perri, Fanny Spagnolo, Pasquale Corsonello, Sebastiano Fabio Schifano, Cristian Zambelli, Angelo Garofalo, Francesco Conti, Luca Benini
2024	J	`jnl`	A High-Speed and Low-Power DSP-Based TRNG for FPGA Implementations. IEEE Trans. Circuits Syst. II Express Briefs Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri
2024	J	`jnl`	An explainable embedded neural system for on-board ship detection from optical satellite imagery. Eng. Appl. Artif. Intell. Cosimo Ieracitano, Nadia Mammone, Fanny Spagnolo, Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Francesco Carlo Morabito
2024	J	`jnl`	Approximate bilateral filters for real-time and low-energy imaging applications on FPGAs. J. Supercomput. Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2024	—	`conf`	Digital In-Memory Computing to Accelerate Deep Learning Inference on the Edge. IPDPS (Workshops) Stefania Perri, Cristian Zambelli, Daniele Ielmini, Cristina Silvano
2024	J	`jnl`	Efficient implementation of signed multipliers on FPGAs. Comput. Electr. Eng. Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2024	J	`jnl`	Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. IEEE Trans. Very Large Scale Integr. Syst. Fanny Spagnolo, Stefania Perri, Massimo Vatalaro, Fabio Frustaci, Felice Crupi, Pasquale Corsonello
2024	B	`conf`	KIT: Kernel Isotropic Transformation of Bilateral Filters for Image Denoising on FPGA. FPL Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2024	—	`conf`	RAW 2024 Invited Talk-2: Digital In-Memory Computing to Accelerate Deep Learning Inference on the Edge. IPDPS (Workshops) Stefania Perri
2023	J	`jnl`	A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers. IEEE Trans. Circuits Syst. II Express Briefs Fabio Frustaci, Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
2023	J	`jnl`	A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms. CoRR Cristina Silvano, Daniele Ielmini, Fabrizio Ferrandi, Leandro Fiorin, Serena Curzel, Luca Benini, Francesco Conti, Angelo Garofalo, Cristian Zambelli, Enrico Calore, Sebastiano Fabio Schifano, Maurizio Palesi, Giuseppe Ascia, Davide Patti, Stefania Perri, Nicola Petra, Davide De Caro, Luciano Lavagno, Teodoro Urso, Valeria Cardellini, Gian Carlo Cardarilli, Robert Birke
2023	J	`jnl`	A Survey on Design Methodologies for Accelerating Deep Learning on Heterogeneous Architectures. CoRR Fabrizio Ferrandi, Serena Curzel, Leandro Fiorin, Daniele Ielmini, Cristina Silvano, Francesco Conti, Alessio Burrello, Francesco Barchi, Luca Benini, Luciano Lavagno, Teodoro Urso, Enrico Calore, Sebastiano Fabio Schifano, Cristian Zambelli, Maurizio Palesi, Giuseppe Ascia, Enrico Russo, Nicola Petra, Davide De Caro, Gennaro Di Meo, Valeria Cardellini, Salvatore Filippone, Francesco Lo Presti, Francesco Silvestri, Paolo Palazzari, Stefania Perri
2023	J	`jnl`	Design of Approximate Bilateral Filters for Image Denoising on FPGAs. IEEE Access Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2023	J	`jnl`	Design of Leading Zero Counters on FPGAs. IEEE Embed. Syst. Lett. Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
2023	J	`jnl`	FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis. J. Signal Process. Syst. Cristian Sestito, Stefania Perri, Robert J. Stewart
2022	B	`conf`	Accuracy Evaluation of Transposed Convolution-Based Quantized Neural Networks. IJCNN Cristian Sestito, Stefania Perri, Robert J. Stewart
2022	J	`jnl`	Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations. IEEE Trans. Circuits Syst. II Express Briefs Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
2022	J	`jnl`	Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems. IEEE Access Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
2022	—	`conf`	Design-Space Exploration of Quantized Transposed Convolutional Neural Networks for FPGA-based Systems-on-Chip. DASC/PiCom/CBDCom/CyberSciTech Cristian Sestito, Stefania Perri, Robert J. Stewart
2022	J	`jnl`	Multibit Full Comparator Logic in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
2022	J	`jnl`	Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes. Sensors Fabio Frustaci, Fanny Spagnolo, Stefania Perri, Giuseppe Cocorullo, Pasquale Corsonello
2022	—	`conf`	Runtime Reconfigurable Hardware Accelerator for Energy-Efficient Transposed Convolutions. PRIME Emanuel Marrazzo, Fanny Spagnolo, Stefania Perri
2021	J	`jnl`	Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA. IEEE Trans. Circuits Syst. II Express Briefs Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
2021	J	`jnl`	Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions. J. Imaging Cristian Sestito, Fanny Spagnolo, Stefania Perri
2020	—	`conf`	A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs. ICECS Fanny Spagnolo, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2020	—	`conf`	An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling. ASAP Cristian Sestito, Fanny Spagnolo, Pasquale Corsonello, Stefania Perri
2020	J	`jnl`	Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation. IEEE Trans. Circuits Syst. Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto
2020	J	`jnl`	Design of a real-time face detection architecture for heterogeneous systems-on-chips. Integr. Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
2020	J	`jnl`	Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip. J. Imaging Stefania Perri, Cristian Sestito, Fanny Spagnolo, Pasquale Corsonello
2020	J	`jnl`	Parallel architecture of power-of-two multipliers for FPGAs. IET Circuits Devices Syst. Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
2020	—	`conf`	Reconfigurable Convolution Architecture for Heterogeneous Systems-on-Chip. MECO Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
2020	J	`jnl`	Stereo vision architecture for heterogeneous systems-on-chip. J. Real Time Image Process. Stefania Perri, Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello
2019	J	`jnl`	An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis. Sensors Fanny Spagnolo, Stefania Perri, Pasquale Corsonello
2019	—	`conf`	Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs. PRIME Fanny Spagnolo, Pasquale Corsonello, Stefania Perri
2019	J	`jnl`	Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. IEEE Trans. Very Large Scale Integr. Syst. Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto
2019	J	`jnl`	Multimodal background subtraction for high-performance embedded systems. J. Real Time Image Process. Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Lorena-de-los-Angeles Guachi-Guachi, Stefania Perri
2018	—	`conf`	Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems. ICECS Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
2018	C	`conf`	Design of Real-Time FPGA-based Embedded System for Stereo Vision. ISCAS Stefania Perri, Fabio Frustaci, Fanny Spagnolo, Pasquale Corsonello
2018	—	`conf`	Designing Fast Convolutional Engines for Deep Learning Applications. ICECS Fanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello
2017	J	`jnl`	Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. IEEE Trans. Circuits Syst. II Express Briefs Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2016	J	`jnl`	An efficient hardware-oriented stereo matching algorithm. Microprocess. Microsystems Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2016	J	`jnl`	Design of efficient QCA multiplexers. Int. J. Circuit Theory Appl. Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2015	C	`conf`	Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology. ICCD Pasquale Corsonello, Stefania Perri, Fabio Frustaci
2015	J	`jnl`	Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. IEEE Trans. Very Large Scale Integr. Syst. Marco Lanuzza, Pasquale Corsonello, Stefania Perri
2015	J	`jnl`	Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology. IEEE Trans. Very Large Scale Integr. Syst. Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2015	J	`jnl`	Power supply noise in accurate delay model for the sub-threshold domain. Integr. Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2014	—	`conf`	A novel background subtraction method based on color invariants and grayscale levels. ICCST Lorena Guachi, Giuseppe Cocorullo, Pasquale Corsonello, Fabio Frustaci, Stefania Perri
2014	J	`jnl`	Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int. J. Circuit Theory Appl. Fabio Frustaci, Marco Lanuzza, Stefania Perri, Pasquale Corsonello
2014	J	`jnl`	Area-Delay Efficient Binary Adders in QCA. IEEE Trans. Very Large Scale Integr. Syst. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
2014	J	`jnl`	Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circuit Theory Appl. Stefania Perri, Marco Lanuzza, Pasquale Corsonello
2014	J	`jnl`	Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. Int. J. Circuit Theory Appl. Pasquale Corsonello, Marco Lanuzza, Stefania Perri
2014	J	`jnl`	Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. IEEE Trans. Circuits Syst. I Regul. Pap. Pasquale Corsonello, Fabio Frustaci, Marco Lanuzza, Stefania Perri
2013	J	`jnl`	Adaptive Census Transform: A novel hardware-oriented stereovision algorithm. Comput. Vis. Image Underst. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
2012	J	`jnl`	Analytical Delay Model Considering Variability Effects in Subthreshold Domain. IEEE Trans. Circuits Syst. II Express Briefs Fabio Frustaci, Pasquale Corsonello, Stefania Perri
2012	J	`jnl`	Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2012	J	`jnl`	Energy-efficient single-clock-cycle binary comparator. Int. J. Circuit Theory Appl. Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
2012	J	`jnl`	Low-Power Level Shifter for Multi-Supply Voltage Designs. IEEE Trans. Circuits Syst. II Express Briefs Marco Lanuzza, Pasquale Corsonello, Stefania Perri
2012	J	`jnl`	Low-cost FPGA stereo vision system for real time disparity maps calculation. Microprocess. Microsystems Paolo Zicari, Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
2011	J	`jnl`	Efficient memory architecture for image processing. Int. J. Circuit Theory Appl. Stefania Perri, Pasquale Corsonello
2011	J	`jnl`	Fast-squarer circuits using 3-bit-scan without overlapping bits. Int. J. Circuit Theory Appl. Stefania Perri, Pasquale Corsonello
2010	C	`conf`	A new low-power high-speed single-clock-cycle binary comparator. ISCAS Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
2010	J	`jnl`	Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM Trans. Reconfigurable Technol. Syst. Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2010	—	`conf`	Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2010	—	`conf`	Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2009	—	`conf`	An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2009	J	`jnl`	Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2009	Misc	`conf`	Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2009	J	`jnl`	Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II Express Briefs Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
2009	J	`jnl`	Low-power split-path data-driven dynamic logic. IET Circuits Devices Syst. Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
2008	—	`conf`	A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation. PATMOS Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
2008	J	`jnl`	A matrix product accelerator for field programmable systems on chip. Microprocess. Microsystems Paolo Zicari, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
2008	J	`jnl`	A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals. Microprocess. Microsystems Paolo Zicari, Emanuele Sciagura, Stefania Perri, Pasquale Corsonello
2008	—	`conf`	Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2008	J	`jnl`	Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator. IEEE Trans. Circuits Syst. II Express Briefs Stefania Perri, Pasquale Corsonello
2008	J	`jnl`	High-performance noise-tolerant circuit techniques for CMOS dynamic logic. IET Circuits Devices Syst. Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
2007	—	`conf`	A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2007	C	`conf`	An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector. DSD Emanuele Sciagura, Paolo Zicari, Stefania Perri, Pasquale Corsonello
2007	C	`conf`	Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
2007	—	`conf`	MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. SAMOS Marco Lanuzza, Stefania Perri, Pasquale Corsonello
2007	J	`jnl`	VLSI implementations of efficient isotropic flexible 2D convolvers. IET Circuits Devices Syst. Stefania Perri, Pasquale Corsonello
2006	—	`conf`	An Efficient Bit-Detection and Timing Recovery Circuit for FPGAs. ICECS Paolo Zicari, Pasquale Corsonello, Stefania Perri
2006	C	`conf`	An integrated countermeasure against differential power analysis for secure smart-cards. ISCAS Pasquale Corsonello, Stefania Perri, Martin Margala
2006	C	`conf`	Leakage energy reduction techniques in deep submicron cache memories: a comparative study. ISCAS Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
2006	J	`jnl`	Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Technol. Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
2006	—	`conf`	SAD-Based Stereo Matching Circuit for FPGAs. ICECS Stefania Perri, Daniela Colonna, Paolo Zicari, Pasquale Corsonello
2006	J	`jnl`	Simd Multipliers for Accelerating Embedded Processors in FPGAS. J. Circuits Syst. Comput. Stefania Perri, Maria Antonia Iachino, Pasquale Corsonello
2006	J	`jnl`	Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories. IEEE Trans. Very Large Scale Integr. Syst. Fabio Frustaci, Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
2005	J	`jnl`	A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsystems Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo
2005	J	`jnl`	Efficient Addition Circuits for Modular Design of Processors-in-Memory. IEEE Trans. Circuits Syst. I Regul. Pap. Pasquale Corsonello, Stefania Perri, Martin Margala
2005	J	`jnl`	Efficient Reconfigurable Manchester Adders for Low-power Media Processing. J. Circuits Syst. Comput. Pasquale Corsonello, Stefania Perri
2005	—	`conf`	Fast Low-Power 64-Bit Modular Hybrid Adder. PATMOS Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
2005	B	`conf`	Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello
2005	J	`jnl`	Microprocessor-based FPGA implementation of SPIHT image compression subsystems. Microprocess. Microsystems Pasquale Corsonello, Stefania Perri, Paolo Zicari, Giuseppe Cocorullo
2004	—	`conf`	Area- and Power-Reduced Standard-Cell Spanning Tree Adders. ESA/VLSI Pasquale Corsonello, Stefania Perri, Vitit Kantabutra
2004	J	`jnl`	Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. Very Large Scale Integr. Syst. Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo
2003	J	`jnl`	A high-speed energy-efficient 64-bit reconfigurable binary adder. IEEE Trans. Very Large Scale Integr. Syst. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
2003	—	`conf`	A low-power sub-nanosecond standard-cells based adder. ICECS Stefania Perri, Pasquale Corsonello, Giovanni Staino
2003	B	`conf`	Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems. FPL Pasquale Corsonello, Stefania Perri, Maria Antonia Iachino, Giuseppe Cocorullo
2002	—	`conf`	Speed-efficient wide adders for VIRTEX FPGAs. ICECS Stefania Perri, Maria Antonia Iachino, Pasquale Corsonello
2002	J	`jnl`	VLSI circuits for low-power high-speed asynchronous addition. IEEE Trans. Very Large Scale Integr. Syst. Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
2001	—	`conf`	Dynamic power of CMOS gates driving lossy transmission lines. ICECS Gregorio Cappuccino, Pasquale Corsonello, Giuseppe Cocorullo, Stefania Perri, Giovanni Staino
2001	—	`conf`	VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits. ICECS Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo, Gregorio Cappuccino, Giovanni Staino
2000	J	`jnl`	Area-time-power tradeoff in cellular arrays VLSI implementations. IEEE Trans. Very Large Scale Integr. Syst. Pasquale Corsonello, Stefania Perri, G. Cororullo
2000	—	`conf`	Designing High-Speed Asynchronous Pipelines. EUROMICRO Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo
2000	—	`conf`	VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. PATMOS Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo
1999	—	`conf`	A 56-bit self-timed adder for high speed asynchronous datapath. ICECS Pasquale Corsonello, Stefania Perri, Giuseppe Cocorullo