Stefan Wildermann

122 papers A* 3A 9B 10C 11Misc 8Journal 29Unranked 46

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Breaking Confidentiality of XTS-AES Encrypted Data at Rest on Microprocessors Using Electromagnetic Side-Channel Attacks. HOST Paul Krüger, Stefan Wildermann, Jürgen Teich
2025	—	`conf`	CHaOS: A Persistent Lightweight Cache Hybridization-Aware OS. ARCS Nils Wilbert, Matthias Szymanski, Stefan Wildermann, Henriette Herzog, Timo Hönig, Jürgen Teich
2025	—	`conf`	FSST Compression of JSON Data on FPGAs. ARCS Tobias Hahn, Jan Hofmann, Stefan Wildermann, Jürgen Teich
2025	J	`jnl`	Modeling and Simulating Emerging Memory Technologies: A Tutorial. CoRR Yun-Chih Chen, Tristan Taylan Seidl, Nils Hölscher, Christian Hakert, Minh Duy Truong, Jian-Jia Chen, João Paulo C. de Lima, Asif Ali Khan, Jerónimo Castrillón, Ali Nezhadi, Lokesh Siddhu, Hassan Nassar, Mahta Mayahinia, Mehdi Baradaran Tahoori, Jörg Henkel, Nils Wilbert, Stefan Wildermann, Jürgen Teich
2025	Misc	`conf`	ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis. BTW Tobias Hahn, Maximilian S. Langohr, Stefan Meißner, Benedikt Döring, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich
2025	—	`conf`	Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs. ASP-DAC Khalil Esper, Stefan Wildermann, Jürgen Teich
2025	—	`conf`	Run-Time Requirement Enforcement of Safety Requirements of Human-Robot Interactions. ICARA Khalil Esper, Stefan Wildermann, Jürgen Teich
2025	—	`conf`	Self-powered Embedded Systems: The Role of Non-volatile Memory Technology in IoT Devices. Go Where the Bugs Are Stefan Wildermann, Nils Wilbert, Tobias Häberlein, Jürgen Teich
2025	—	`ed.`	Sixth Workshop on Next Generation Real-Time Embedded Systems, NG-RES 2025, Barcelona, Spain, January 20, 2025 NG-RES@HiPEAC Patrick Meumeu Yomsi, Stefan Wildermann
2024	J	`jnl`	A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs. ACM Trans. Design Autom. Electr. Syst. Jan Spieck, Stefan Wildermann, Jürgen Teich
2024	C	`conf`	ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs. DDECS Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich
2024	—	`conf`	CRESTS: Chronology-based Reconstruction for Side-Channel Trace Segmentation for XTS-AES on Complex Targets. EuroSec@EUROSYS Paul Krüger, Stefan Wildermann, Jürgen Teich
2024	J	`jnl`	Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s. ACM Trans. Reconfigurable Technol. Syst. Jens Trautmann, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
2024	—	`ed.`	Fifth Workshop on Next Generation Real-Time Embedded Systems, NG-RES 2024, Munich, Germany, January 17-19, 2024 NG-RES@HiPEAC Patrick Meumeu Yomsi, Stefan Wildermann
2024	—	`conf`	GRES: Guaranteed Remaining Energy Scheduling of Energy-harvesting Sensors by Quality Adaptation. MECO Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich
2024	—	`conf`	Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study. MEMSYS Nils Wilbert, Stefan Wildermann, Jürgen Teich
2024	B	`conf`	JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs. FPL Tobias Hahn, Stefan Wildermann, Jürgen Teich
2024	A	`conf`	Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. DATE Khalil Esper, Stefan Wildermann, Jürgen Teich
2024	—	`conf`	To Keep or Not to Keep - The Volatility of Replacement Policy Metadata in Hybrid Caches. DIMES@SOSP Nils Wilbert, Stefan Wildermann, Jürgen Teich
2023	J	`jnl`	A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs. ACM Trans. Design Autom. Electr. Syst. Jan Spieck, Stefan Wildermann, Jürgen Teich
2023	Misc	`conf`	An FPGA Avro Parser Generator for Accelerated Data Stream Processing. BTW Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich
2023	—	`ed.`	Architecture of Computing Systems - 36th International Conference, ARCS 2023, Athens, Greece, June 13-15, 2023, Proceedings ARCS Georgios I. Goumas, Sven Tomforde, Jürgen Brehm, Stefan Wildermann, Thilo Pionteck
2023	J	`jnl`	Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms. ACM Trans. Design Autom. Electr. Syst. Khalil Esper, Stefan Wildermann, Jürgen Teich
2023	C	`conf`	Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. MEMOCODE Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann, Jürgen Teich
2023	—	`conf`	RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs. NG-RES@HiPEAC Khalil Esper, Jan Spieck, Pierre-Louis Sixdenier, Stefan Wildermann, Jürgen Teich
2023	B	`conf`	SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. FPL Tobias Hahn, Stefan Wildermann, Jürgen Teich
2023	—	`conf`	Seque: Lean and Energy-aware Data Management for IoT Gateways. EDGE Pierre-Louis Sixdenier, Stefan Wildermann, Martin Ottens, Jürgen Teich
2023	Misc	`conf`	Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng
2022	B	`conf`	Auto-Tuning of Raw Filters for FPGAs. FPL Tobias Hahn, Stefan Wildermann, Jürgen Teich
2022	Misc	`conf`	Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. FCCM Jens Trautmann, Jürgen Teich, Stefan Wildermann
2022	J	`jnl`	Design and Evaluation of a Tunable PUF Architecture for FPGAs. ACM Trans. Reconfigurable Technol. Syst. Franz-Josef Streit, Paul Krüger, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	J	`jnl`	Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains. it Inf. Technol. Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
2022	—	`conf`	Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study. NG-RES@HiPEAC Khalil Esper, Stefan Wildermann, Jürgen Teich
2022	J	`jnl`	On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jan Spieck, Stefan Wildermann, Jürgen Teich
2022	—	`conf`	Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. ASHES@CCS Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	A	`conf`	Raw Filtering of JSON Data on FPGAs. DATE Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	J	`jnl`	Raw Filtering of JSON Data on FPGAs. CoRR Tobias Hahn, Andreas Becher, Stefan Wildermann, Jürgen Teich
2022	B	`conf`	Real-Time Waveform Matching with a Digitizer at 10 GS/s. FPL Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
2022	J	`jnl`	Real-Time Waveform Matching with a Digitizer at 10 GS/s. CoRR Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jürgen Teich, Stefan Wildermann
2022	—	`conf`	SIDAM: A Design Space Exploration Framework for Multi-sensor Embedded Systems Powered by Energy Harvesting. SAMOS Pierre-Louis Sixdenier, Stefan Wildermann, Daniel Ziegler, Jürgen Teich
2022	J	`jnl`	Semi-Automatic Locating of Cryptographic Operations in Side-Channel Traces. IACR Trans. Cryptogr. Hardw. Embed. Syst. Jens Trautmann, Arthur Beckers, Lennert Wouters, Stefan Wildermann, Ingrid Verbauwhede, Jürgen Teich
2022	J	`jnl`	Task Migration Policy for Thermal-Aware Dynamic Performance Optimization in Many-Core Systems. IEEE Access Behnaz Pourmohseni, Stefan Wildermann, Fedor Smirnov, Paul E. Meyer, Jürgen Teich
2021	—	`conf`	A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper). NG-RES@HiPEAC Khalil Esper, Stefan Wildermann, Jürgen Teich
2021	A	`conf`	Approximate Logic Synthesis of Very Large Boolean Networks. DATE Jorge Echavarria, Stefan Wildermann, Jürgen Teich
2021	—	`conf`	CORSICA: A Framework for Conducting Real-World Side-Channel Analysis. NTMS Jens Schlumberger, Stefan Wildermann, Jürgen Teich
2021	B	`conf`	Choice - A Tunable PUF-Design for FPGAs. FPL Franz-Josef Streit, Paul Krüger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jürgen Teich
2021	—	`conf`	Domain-Adaptive Soft Real-Time Hybrid Application Mapping for MPSoCs. MLCAD Jan Spieck, Stefan Wildermann, Jürgen Teich
2021	C	`conf`	Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. MEMOCODE Khalil Esper, Stefan Wildermann, Jürgen Teich
2021	J	`jnl`	On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains. CoRR Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Faramarz Khosravi, Andreas Becher, Jürgen Teich
2021	—	`conf`	Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware. ARC Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk, Jürgen Teich
2021	—	`conf`	Run-Time Enforcement of Non-functional Program Properties on MPSoCs. A Journey of Embedded and Cyber-Physical Systems Jürgen Teich, Pouya Mahmoody, Behnaz Pourmohseni, Sascha Roloff, Wolfgang Schröder-Preikschat, Stefan Wildermann
2021	J	`jnl`	Speculative Dynamic Reconfiguration and Table Prefetching Using Query Look-Ahead in the ReProVide Near-Data-Processing System. Datenbank-Spektrum Lekshmi Beena Gopalakrishnan Nair, Andreas Becher, Stefan Wildermann, Klaus Meyer-Wegener, Jürgen Teich
2020	A*	`conf`	Probabilistic Error Propagation through Approximated Boolean Networks. DAC Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich
2020	—	`conf`	Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems. NG-RES@HiPEAC Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich
2020	—	`conf`	Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. ASP-DAC Jürgen Teich, Behnaz Pourmohseni, Oliver Keszöcze, Jan Spieck, Stefan Wildermann
2020	B	`conf`	SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. EDBT Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jürgen Teich
2020	A*	`conf`	Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. DAC Jan Spieck, Stefan Wildermann, Jürgen Teich
2020	—	`conf`	Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. HOST Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich
2020	J	`jnl`	Secure Boot from Non-Volatile Memory for Programmable SoC Architectures. CoRR Franz-Josef Streit, Florian Fritz, Andreas Becher, Stefan Wildermann, Stefan Werner, Martin Schmidt-Korth, Michael Pschyklenk, Jürgen Teich
2019	J	`jnl`	Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization. ACM Trans. Design Autom. Electr. Syst. Tobias Schwarzer, Joachim Falk, Simone Müller, Martín Letras, Christian Heidorn, Stefan Wildermann, Jürgen Teich
2019	—	`conf`	Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs. ReConFig Patrick Plagwitz, Franz-Josef Streit, Andreas Becher, Stefan Wildermann, Jürgen Teich
2019	—	`conf`	Data-Driven Scenario-Based Application Mapping for Heterogeneous Many-Core Systems. MCSoC Jan Spieck, Stefan Wildermann, Tobias Schwarzer, Jürgen Teich, Michael Glaß
2019	J	`jnl`	Hard real-time application mapping reconfiguration for NoC-based many-core systems. Real Time Syst. Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich
2019	B	`conf`	Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. ECRTS Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich
2019	J	`jnl`	Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. CoRR Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jürgen Teich
2019	—	`conf`	ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. BTW (Workshops) Andreas Becher, Achim Herrmann, Stefan Wildermann, Jürgen Teich
2019	—	`conf`	Resource-Aware Parameter Tuning for Real-Time Applications. ARCS Dirk Gabriel, Walter Stechele, Stefan Wildermann
2019	A	`conf`	Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems. RTSS Behnaz Pourmohseni, Fedor Smirnov, Heba Khdr, Stefan Wildermann, Jürgen Teich, Jörg Henkel
2018	J	`jnl`	A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. ACM Trans. Embed. Comput. Syst. Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich
2018	—	`conf`	AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs. FPT Jorge Echavarria, Stefan Wildermann, Jürgen Teich
2018	A*	`conf`	Architecture decomposition in system synthesis of heterogeneous many-core systems. DAC Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jürgen Teich, Michael Glaß
2018	—	`conf`	Can Approximate Computing Reduce Power Consumption on FPGAs? ICECS Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich
2018	A	`conf`	Design space exploration of multi-output logic function approximations. ICCAD Jorge Echavarria, Stefan Wildermann, Jürgen Teich
2018	A	`conf`	Dynamic resource management for heterogeneous many-cores. ICCAD Jörg Henkel, Jürgen Teich, Stefan Wildermann, Hussam Amrouch
2018	J	`jnl`	Efficient Arithmetic Error Rate Calculus for Visibility Reduced Approximate Adders. IEEE Embed. Syst. Lett. Jorge Echavarria, Stefan Wildermann, Eduard Potwigin, Jürgen Teich
2018	J	`jnl`	Integration of FPGAs in Database Management Systems: Challenges and Opportunities. Datenbank-Spektrum Andreas Becher, Lekshmi B. G., David Broneske, Tobias Drewes, Bala Gurumurthy, Klaus Meyer-Wegener, Thilo Pionteck, Gunter Saake, Jürgen Teich, Stefan Wildermann
2018	—	`book`	Invasive Computing for Mapping Parallel Programs to Many-Core Architectures. Andreas Weichslgartner, Stefan Wildermann, Michael Glaß, Jürgen Teich
2018	—	`conf`	Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs. ReConFig Franz-Josef Streit, Martín Letras, Stefan Wildermann, Benjamin Hackenberg, Joachim Falk, Andreas Becher, Jürgen Teich
2018	—	`conf`	On the Complexity of Mapping Feasibility in Many-Core Architectures. MCSoC Tobias Schwarzer, Sascha Roloff, Valentina Richthammer, Rami Khaldi, Stefan Wildermann, Michael Glaß, Jürgen Teich
2018	C	`conf`	Optimistic regular expression matching on FPGAs for near-data processing. DaMoN Andreas Becher, Stefan Wildermann, Jürgen Teich
2018	J	`jnl`	Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tobias Schwarzer, Andreas Weichslgartner, Michael Glaß, Stefan Wildermann, Peter Brand, Jürgen Teich
2017	J	`jnl`	A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs. CoRR Andreas Weichslgartner, Stefan Wildermann, Deepak Gangadharan, Michael Glaß, Jürgen Teich
2017	C	`conf`	Automatic Conversion of Simulink Models to SysteMoC Actor Networks. SCOPES Martín Letras, Joachim Falk, Stefan Wildermann, Jürgen Teich
2017	C	`conf`	Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems. SCOPES Peter Brand, Jonathan Ah Sue, Johannes Brendel, Joachim Falk, Ralph Hasholzner, Jürgen Teich, Stefan Wildermann
2017	—	`conf`	High-Level Synthesis for Hardware/Software Co-Design of Distributed Smart Camera Systems. ICDSC Franz-Josef Streit, Martín Letras, Matthias Schid, Joachim Falk, Stefan Wildermann, Jürgen Teich
2017	Misc	`conf`	Predictable run-time mapping reconfiguration for real-time applications on many-core systems. RTNS Behnaz Pourmohseni, Stefan Wildermann, Michael Glaß, Jürgen Teich
2017	C	`conf`	Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. SCOPES Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jürgen Teich, Stefan Wildermann
2017	J	`jnl`	Towards the co-evolution of industrial products and its production systems by combining models from development and hardware/software deployment in cyber-physical systems. Prod. Eng. Birgit Vogel-Heuser, Stefan Wildermann, Jürgen Teich
2016	Misc	`conf`	A LUT-Based Approximate Adder. FCCM Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jürgen Teich
2016	—	`conf`	ActorX10: an actor library for X10. X10@PLDI Sascha Roloff, Alexander Pöppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Glaß, Frank Hannig, Jürgen Teich
2016	C	`conf`	Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. SCOPES Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix C. Freiling, Michael Glaß, Jürgen Teich
2016	—	`conf`	FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. FPT Jorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener
2016	—	`conf`	Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs. ReConFig Andreas Becher, Jutta Pirkl, Achim Herrmann, Jürgen Teich, Stefan Wildermann
2016	J	`jnl`	Invasive computing for timing-predictable stream processing on MPSoCs. it Inf. Technol. Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau
2016	—	`conf`	Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing. MCSoC Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner, Stefan Wildermann
2016	J	`jnl`	Providing security on demand using invasive computing. it Inf. Technol. Gabor Drescher, Christoph Erhardt, Felix C. Freiling, Johannes Götzfried, Daniel Lohmann, Pieter Maene, Tilo Müller, Ingrid Verbauwhede, Andreas Weichslgartner, Stefan Wildermann
2016	—	`conf`	ReOrder: Runtime datapath generation for high-throughput multi-stream processing. ReConFig Andreas Becher, Stefan Wildermann, Moritz Mühlenthaler, Jürgen Teich
2015	—	`conf`	Design Methodology and Run-Time Management for Predictable Many-Core Systems. ISORC Workshops Stefan Wildermann, Andreas Weichslgartner, Jürgen Teich
2015	—	`conf`	Invasive computing for predictable stream processing: a simulation-based case study. ESTIMedia Sascha Roloff, Stefan Wildermann, Frank Hannig, Jürgen Teich
2014	Misc	`conf`	DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems. CODES+ISSS Andreas Weichslgartner, Deepak Gangadharan, Stefan Wildermann, Michael Glaß, Jürgen Teich
2014	A	`conf`	Multi-objective distributed run-time resource management for many-cores. DATE Stefan Wildermann, Michael Glaß, Jürgen Teich
2014	—	`conf`	Self-Integration for Virtualization of Embedded Many-Core Systems. SASO Workshops Stefan Wildermann, Jürgen Teich
2013	A	`conf`	Game-theoretic analysis of decentralized core allocation schemes on many-core systems. DATE Stefan Wildermann, Tobias Ziermann, Jürgen Teich
2013	J	`jnl`	Symbolic system-level design methodology for multi-mode reconfigurable systems. Des. Autom. Embed. Syst. Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich
2012	J	`jnl`	Distributed self-organizing bandwidth allocation for priority-based bus communication. Concurr. Comput. Pract. Exp. Tobias Ziermann, Stefan Wildermann, Nina Mühleis, Jürgen Teich
2012	J	`jnl`	Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. Stefan Wildermann, Josef Angermeier, Eugen Sibirko, Jürgen Teich
2012	—	`—`	Systematic design of self-adaptive embedded systems with applications in image processing. Stefan Wildermann
2011	—	`conf`	Dynamic decentralized mapping of tree-structured applications on NoC architectures. NOCS Andreas Weichslgartner, Stefan Wildermann, Jürgen Teich
2011	—	`conf`	Operational mode exploration for reconfigurable systems with multiple applications. FPT Stefan Wildermann, Felix Reimann, Jürgen Teich, Zoran Salcic
2011	—	`ch.`	OrganicBus: Organic Self-organising Bus-Based Communication Systems. Organic Computing Tobias Ziermann, Stefan Wildermann, Jürgen Teich
2011	Misc	`conf`	Symbolic design space exploration for multi-mode reconfigurable systems. CODES+ISSS Stefan Wildermann, Felix Reimann, Daniel Ziener, Jürgen Teich
2011	B	`conf`	Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. FPL Stefan Wildermann, Jürgen Teich, Daniel Ziener
2010	B	`conf`	A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. FPL Andreas Oetken, Stefan Wildermann, Jürgen Teich, Dirk Koch
2010	—	`conf`	A Self-Organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-Based Bus Communication. ISORC Workshops Tobias Ziermann, Nina Mühleis, Stefan Wildermann, Jürgen Teich
2010	—	`conf`	Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures. ReConFig Josef Angermeier, Stefan Wildermann, Eugen Sibirko, Jürgen Teich
2010	C	`conf`	Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras. ATC Stefan Wildermann, Andreas Oetken, Jürgen Teich, Zoran A. Salcic
2009	A	`conf`	CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16× higher data rates. DATE Tobias Ziermann, Stefan Wildermann, Jürgen Teich
2009	—	`conf`	Self-organizing Bandwidth Sharing in Priority-Based Medium Access. SASO Stefan Wildermann, Tobias Ziermann, Jürgen Teich
2009	B	`conf`	Self-organizing multi-cue fusion for FPGA-based embedded imaging. FPL Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jürgen Teich
2008	—	`conf`	3D Person Tracking with a Color-Based Particle Filter. RobVis Stefan Wildermann, Jürgen Teich
2008	C	`conf`	A Sequential Learning Resource Allocation Network for Image Processing Applications. HIS Stefan Wildermann, Jürgen Teich
2008	C	`conf`	Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. IEEE International Workshop on Rapid System Prototyping Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jürgen Teich