Stefan Rusu - RankMe

37 papers A* 1Journal 22Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	K-Means Clustering for Portfolio Optimization: Symmetry in Risk-Return Tradeoff, Liquidity, Profitability, and Solvency. Symmetry Marcel Ioan Bolos, Stefan Rusu, Marius Leordeanu, Diana Claudia Sabau-Popa, Diana Claudia Perticas, Mihai-Ioan Crisan
2025	—	`conf`	TSMC in the Silicon Photonics Era - an Electrical Perspective. OFC Mikael Sahrling, Shenggao Li, Frank Lee, Stefan Rusu
2020	J	`jnl`	A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. IEEE J. Solid State Circuits Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee
2019	—	`conf`	A 7nm 4GHz Arm VLSI Circuits Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee
2019	J	`jnl`	Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits Ángel Rodríguez-Vázquez, Kaushik Sengupta, Stefan Rusu
2019	J	`jnl`	Hot Chips 30. IEEE Micro John Kubiatowicz, Stefan Rusu
2016	J	`jnl`	Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits Andrea Mazzanti, Bram Nauta, Stefan Rusu
2016	—	`conf`	Welcome to 2016 Hot Chips. Hot Chips Symposium Stefan Rusu
2015	J	`jnl`	A 22 nm 15-Core Enterprise Xeon® Processor Family. IEEE J. Solid State Circuits Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang
2015	J	`jnl`	Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Stefan Rusu, Gregory Chen
2014	—	`conf`	5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. ISSCC Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang
2014	J	`jnl`	Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits Yann Deval, Stefan Rusu
2010	J	`jnl`	A 45 nm 8-Core Enterprise Xeon¯ Processor. IEEE J. Solid State Circuits Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora
2009	—	`conf`	A 45nm 8-core enterprise Xeon® processor. ISSCC Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli
2009	J	`jnl`	Introduction to the Special Issue on the 34th ESSCIRC. IEEE J. Solid State Circuits Kari A. I. Halonen, Kofi A. A. Makinwa, Stefan Rusu
2009	—	`conf`	Multi-domain processors. ISSCC Stefan Rusu
2009	—	`conf`	Power reduction techniques for an 8-core xeon® processor. ESSCIRC Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora
2008	J	`jnl`	Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007). IEEE J. Solid State Circuits Andrea Baschirotto, Edoardo Charbon, Stefan Rusu
2008	—	`conf`	Short Course. ISSCC Ian Galton, Jonathan Audy, Vadim Ivanov, Stefan Rusu, Seth R. Sanders
2007	J	`jnl`	A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE J. Solid State Circuits Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora
2007	J	`jnl`	Introduction to the Special Issue on ESSCIRC 2006. IEEE J. Solid State Circuits Andreas Kaiser, Stefan Rusu
2007	—	`conf`	Microprocessors. ISSCC Stefan Rusu, Jim Warnock
2007	J	`jnl`	The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. IEEE J. Solid State Circuits Jonathan Chang, Ming Huang, Jonathan Shoemaker, John Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, Raghuraman Ganesan, Gloria Leong, Venkata Lukka, Stefan Rusu, Durgesh Srivastava
2006	—	`conf`	A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. ISSCC Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang
2005	J	`jnl`	A 130-nm triple-V IEEE J. Solid State Circuits Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni
2005	J	`jnl`	Introduction to the Special Issue on ESSCIRC'2004. IEEE J. Solid State Circuits Rolf Koch, Stefan Rusu
2004	—	`conf`	Clock generation and distribution in high-performance processors. SoC Stefan Rusu
2004	J	`jnl`	Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. IEEE Micro Stefan Rusu, Harry Muljono, Brian S. Cherkauer
2003	J	`jnl`	A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. IEEE J. Solid State Circuits Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer
2003	A*	`conf`	A 1.5GHz third generation itanium® 2 processor. DAC Jason Stinson, Stefan Rusu
2003	J	`jnl`	A 400-MT/s 6.4-GB/s multiprocessor bus interface. IEEE J. Solid State Circuits Harry Muljono, Beom-Taek Lee, Yanmei (Kathy) Tian, Yanbin (Eddie) Wang, Mubeen Atha, Tiffany Huang, Mitsuhiro Adachi, Stefan Rusu
2002	J	`jnl`	Guest editorial. IEEE J. Solid State Circuits Christian C. Enz, Stefan Rusu
2002	—	`conf`	Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). ASP-DAC/VLSI Design Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta
2000	J	`jnl`	Clock generation and distribution for the first IA-64 microprocessor. IEEE J. Solid State Circuits Simon Tam, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, Ian Young
2000	—	`conf`	Itanium processor clock design. ISPD Utpal Desai, Simon M. Tam, Robert Kim, Ji Zhang, Stefan Rusu
2000	J	`jnl`	The first IA-64 microprocessor. IEEE J. Solid State Circuits Stefan Rusu, Gadi Singer
1993	—	`conf`	TONIC: A timing database for VLSI design. EURO-DAC Gregory Schulte, Peter Tong, Stefan Rusu, Stuart Taylor