Stefan Pechmann

15 papers C 1Journal 1Unranked 13
YearRankTypeTitle / Venue / Authors
2025 — conf
A Fast Reading Method for Multi-Level RRAM in Small-Scale Arrays.
ICECS
Running Guo, Keyu Liu, Stefan Pechmann, Amelie Hagelauer
2025 — conf
A Reading Scheme for 3T3R RRAM and Their Arrays Recognizing 64 States.
ICECS
Running Guo, Stefan Pechmann, Amelie Hagelauer
2025 C conf
Fully-Integrated Differential RRAM Cell Designs with Multi-Level Capability and Enhanced Read Margin.
ISCAS
Stefan Pechmann, Peter Reichel, Thorsten Spätling, Amelie Hagelauer
2024 — conf
A Current Mirror Based Read Circuit Design with Multi-Level Capability for Resistive Switching Devices.
ICEIC
Stefan Pechmann, Eduardo Pérez, Christian Wenger, Amelie Hagelauer
2024 — conf
A Reading Method for 2T2R RRAM Arrays Coding their Multiple States.
MWSCAS
Running Guo, Stefan Pechmann, Amelie Hagelauer
2024 — conf
A Structured Approach for Embedded Memory Integration of Emerging Memory Technologies.
LASCAS
Stefan Pechmann, Thorsten Spätling, Peter Reichel, Roland Müller, Amelie Hagelauer
2024 — conf
Soft-Error Analysis of RRAM 1T1R Compute-In-Memory Core for Artificial Neural Networks.
DCIS
Ruolan Jia, Stefan Pechmann, Markus Fritscher, Christian Wenger, Lei Zhang, Amelie Hagelauer
2023 — conf
A High-speed Low-power Sense Amplifier for the RRAM Array with Multi-level Reading Function using 130-nm Technology.
ICECS
Running Guo, Ruolan Jia, Stefan Pechmann, Marc Reichenbach, Amelie Hagelauer
2023 — conf
A RRAM Characterization System with Flexible Readout Operations using an Integrating ADC.
PRIME
Ruolan Jia, Stefan Pechmann, Andrea Baroni, Christian Wenger, Amelie Hagelauer
2022 — conf
A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays.
SOCC
Stefan Pechmann, Amelie Hagelauer
2022 — conf
A Read Circuit Design for Multi-Level RRAM Cells Exhibiting Small Resistance Windows.
MWSCAS
Stefan Pechmann, Amelie Hagelauer
2021 J jnl
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates.
IEEE Trans. Very Large Scale Integr. Syst.
John Reuben, Stefan Pechmann
2021 — conf
Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks.
SAMOS
Markus Fritscher, Johannes Knödtel, Maen Mallah, Stefan Pechmann, Emilio Pérez-Bosch Quesada, Tommaso Rizzi, Christian Wenger, Marc Reichenbach
2021 — conf
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations.
LASCAS
Markus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach
2020 — conf
A Parallel-friendly Majority Gate to Accelerate In-memory Computation.
ASAP
John Reuben, Stefan Pechmann