Stanley Schuster

13 papers A 1Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2009 J jnl
Fast Low Power eDRAM Hierarchical Differential Sense Amplifier.
IEEE J. Solid State Circuits
Stanley Schuster, Richard E. Matick
2008 J jnl
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2007 — conf
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
ISSCC
John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer
2005 J jnl
Logic-based eDRAM: Origins and rationale for use.
IBM J. Res. Dev.
Richard E. Matick, Stanley Schuster
2003 J jnl
Dynamically Tuning Processor Resources with Adaptive Processing.
Computer
David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
2003 J jnl
Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz.
IEEE J. Solid State Circuits
Stanley Schuster, Peter W. Cook
2002 — conf
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
PACS
Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
2002 — conf
Synchronous Interlocked Pipelines.
ASYNC
Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster
2002 A conf
Tradeoffs in power-efficient issue queue design.
ISLPED
Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster
2001 — conf
A circuit level implementation of an adaptive issue queue for power-aware microprocessors.
ACM Great Lakes Symposium on VLSI
Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook
2000 — conf
An Adaptive Issue Queue for Reduced Power at High Performance.
PACS
Alper Buyuktosunoglu, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi
2000 J jnl
Design and characteristics of n-channel insulated-gate field-effect transistors.
IBM J. Res. Dev.
Dale L. Critchlow, Robert H. Dennard, Stanley Schuster
2000 J jnl
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors.
IEEE Micro
David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook