Stanislaw J. Piestrak

60 papers A 1C 14Misc 2Journal 26Unranked 16
YearRankTypeTitle / Venue / Authors
2025 J jnl
Efficient Implementations of Residue Generators Mod 2n + 1 Providing Diminished-1 Representation.
CoRR
Stanislaw J. Piestrak, Piotr Patronik
2023 J jnl
Design of reverse converters for the general RNS 3-moduli set {2
EURASIP J. Adv. Signal Process.
Piotr Patronik, Stanislaw J. Piestrak
2018 J jnl
Correction to: Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2
Circuits Syst. Signal Process.
Piotr Patronik, Stanislaw J. Piestrak
2018 J jnl
Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels.
J. Signal Process. Syst.
Piotr Patronik, Stanislaw J. Piestrak
2017 J jnl
Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2
Circuits Syst. Signal Process.
Piotr Patronik, Stanislaw J. Piestrak
2017 — conf
Design of residue generators with CLA/compressor trees and multi-bit EAC.
LASCAS
Piotr Patronik, Stanislaw J. Piestrak
2017 J jnl
Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units.
IEEE Trans. Circuits Syst. I Regul. Pap.
Piotr Patronik, Stanislaw J. Piestrak
2016 — conf
Design of a low-power RNS-enhanced arithmetic unit.
LASCAS
Piotr Patronik, Stanislaw J. Piestrak
2015 J jnl
A note on RNS architectures for the implementation of the diagonal function.
Inf. Process. Lett.
Stanislaw J. Piestrak
2015 C conf
Fault-aware configurable logic block for reliable reconfigurable FPGAs.
ISCAS
B. Chagun Basha, Sébastien Pillement, Stanislaw J. Piestrak
2015 — conf
Fault-tolerant implementation of direct FIR filters protected using residue codes.
NORCAS
Stanislaw J. Piestrak, Piotr Patronik
2014 — conf
Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs.
ARC
B. Chagun Basha, Stanislaw J. Piestrak, Sébastien Pillement
2014 C conf
Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes.
DSD
Stanislaw J. Piestrak, Piotr Patronik
2014 J jnl
Design of Reverse Converters for General RNS Moduli Sets {2
IEEE Trans. Circuits Syst. I Regul. Pap.
Piotr Patronik, Stanislaw J. Piestrak
2014 J jnl
Design of Reverse Converters for the New RNS Moduli Set {2
IEEE Trans. Circuits Syst. I Regul. Pap.
Piotr Patronik, Stanislaw J. Piestrak
2014 J jnl
Design of the coarse-grained reconfigurable architecture DART with on-line error detection.
Microprocess. Microsystems
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
2014 J jnl
Private reliability environments for efficient fault-tolerance in CGRAs.
Des. Autom. Embed. Syst.
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2013 C conf
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs.
DSD
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
2013 — conf
Implementation and evaluation of configuration scrubbing on CGRAs: A case study.
ISSoC
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2013 J jnl
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor.
IEEE Trans. Computers
Hung-Manh Pham, Sébastien Pillement, Stanislaw J. Piestrak
2012 — conf
Design of an RNS reverse converter for a new five-moduli special set.
ACM Great Lakes Symposium on VLSI
Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava
2011 C conf
Design of multi-residue generators using shared logic.
ISCAS
Stanislaw J. Piestrak
2011 C conf
Error recovery technique for coarse-grained reconfigurable architectures.
DDECS
Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
2011 A conf
Fast and energy-efficient constant-coefficient FIR filters using residue number system.
ISLPED
Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava
2010 J jnl
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication".
IEEE Commun. Lett.
Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys
2010 — conf
Design of a fault-tolerant coarse-grained.
ISQED
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement
2010 C conf
Design of cost-efficient multipliers modulo 2
ISCAS
Stanislaw J. Piestrak
2010 J jnl
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication.
IEEE Trans. Circuits Syst. II Express Briefs
Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys
2010 C conf
On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels.
DSD
Stanislaw J. Piestrak
2009 J jnl
Design of parallel fault-secure encoders for systematic cyclic block transmission codes.
Microelectron. J.
Houssein Jaber, Fabrice Monteiro, Stanislaw J. Piestrak, Abbas Dandache
2009 Misc conf
Exploiting residue number system for power-efficient digital signal processing in embedded processors.
CASES
Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak
2007 C conf
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes.
IOLTS
Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache
2006 C conf
Characterizing Laser-Induced Pulses in ICs: Methodology and Results.
IOLTS
Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache, Stéphane Rossignol, Pascal Moitrel
2005 C conf
Modeling of Transients Caused by a Laser Attack on Smart Cards.
IOLTS
Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache
2003 J jnl
Designing fault-secure parallel encoders for systematic linear error correcting codes.
IEEE Trans. Reliab.
Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
2002 J jnl
Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'.
IEEE Trans. Computers
Stanislaw J. Piestrak
2002 J jnl
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes.
IEEE Trans. Computers
Stanislaw J. Piestrak
2002 — conf
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage.
DFT
Stanislaw J. Piestrak
2001 — conf
Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes.
DFT
Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro
2001 — conf
On the Design of Self-Testing Checkers for Modified Berger Codes.
IOLTW
Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos
1999 Misc conf
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits.
EDCC
Jerzy W. Greblicki, Stanislaw J. Piestrak
1998 J jnl
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters.
J. Electron. Test.
Stanislaw J. Piestrak
1998 — conf
Membership Test Logic for Delay-Insensitive Codes.
ASYNC
Stanislaw J. Piestrak
1998 — conf
VLSI implementation and complexity comparison of residue generators modulo 3.
EUSIPCO
Stanislaw J. Piestrak, Fabrice Pedron, Olivier Sentieys
1997 — conf
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes.
DFT
Stanislaw J. Piestrak
1996 J jnl
Design of Self-Testing Checkers for Borden Codes.
IEEE Trans. Computers
Stanislaw J. Piestrak
1996 J jnl
Design of minimal-level PLA self-testing checkers for m-out-of-n codes.
IEEE Trans. Very Large Scale Integr. Syst.
Stanislaw J. Piestrak
1996 J jnl
Self-Checking Design in Eastern Europe.
IEEE Des. Test Comput.
Stanislaw J. Piestrak
1995 — —
Design of self-testing checkers for unidirectional error detecting codes.
Stanislaw J. Piestrak
1995 — conf
Towards Totally Self-Checking Delay-Insensitive Systems.
FTCS
Stanislaw J. Piestrak, Takashi Nanya
1994 C conf
Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem.
ICCD
Stanislaw J. Piestrak
1994 J jnl
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders.
IEEE Trans. Computers
Stanislaw J. Piestrak
1994 C conf
Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes.
ICCD
Stanislaw J. Piestrak
1993 J jnl
The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks.
IEEE Trans. Computers
Stanislaw J. Piestrak
1991 C conf
Design of a Self-Testing Checker for Borden Code.
ICCD
Stanislaw J. Piestrak
1991 C conf
Design of residue generators and multioperand modular adders using carry-save adders.
IEEE Symposium on Computer Arithmetic
Stanislaw J. Piestrak
1991 — conf
Efficient Encoding? Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes.
Fault-Tolerant Computing Systems
Stanislaw J. Piestrak
1990 J jnl
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes.
IEEE Trans. Computers
Stanislaw J. Piestrak
1990 — conf
The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes.
FTCS
Stanislaw J. Piestrak
1987 J jnl
Design of Fast Self-Testing Checkers for a Class of Berger Codes.
IEEE Trans. Computers
Stanislaw J. Piestrak