Srivaths Ravi - RankMe

117 papers A* 9A 26B 2C 3Misc 25Journal 39Unranked 13

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing. J. Electron. Test. Isaac Bruce, Praise O. Farayola, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2023	J	`jnl`	Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction. IEEE Des. Test Praise O. Farayola, Ekaniyere Oko-Odion, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2022	J	`jnl`	A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing. J. Electron. Test. Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2022	—	`conf`	Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing. DFT Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2022	B	`conf`	Graph Theory Approach for Multi-site ATE Board Parameter Extraction. ETS Abraham Steenhoek, Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2022	A	`conf`	Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing. ITC Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2022	Misc	`conf`	The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing. VTS Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2021	B	`conf`	An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study. ETS Isaac Bruce, Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2021	J	`jnl`	Detection of Site to Site Variations From Volume Measurement Data in Multisite Semiconductor Testing. IEEE Trans. Instrum. Meas. Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2021	—	`conf`	Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation. DTIS Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2021	A	`conf`	Systematic Hardware Error Identification and Calibration for Massive Multisite Testing. ITC Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2020	Misc	`conf`	Quantile - Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing. VTS Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
2017	A	`conf`	Demystifying automotive safety and security for semiconductor developer. ITC V. Prasanth, David Foley, Srivaths Ravi
2017	Misc	`conf`	Foreword. VTS Yiorgos Makris, Srivaths Ravi, Amit Majumdar
2015	Misc	`conf`	Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems. VLSID Prabhat Mishra, Swarup Bhunia, Srivaths Ravi
2014	A	`conf`	At-speed capture power reduction using layout-aware granular clock gate enable controls. ITC Raashid Shaikh, Pradeep Wilson, Khushboo Agarwal, H. V. Sanjay, Rajesh Tiwari, Kaushik Lath, Srivaths Ravi
2014	—	`conf`	Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs. ATS Chandan Kumar, Fadi Maamari, Kiran Vittal, Wilson Pradeep, Rajesh Tiwari, Srivaths Ravi
2014	Misc	`conf`	Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. VLSID Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula
2011	J	`jnl`	Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. J. Low Power Electron. Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi
2011	Misc	`conf`	Multi-CoDec Configurations for Low Power and High Quality Scan Test. VLSI Design Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi
2010	Misc	`conf`	A generic low power scan chain wrapper for designs using scan compression. VTS Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji
2010	A	`conf`	Methodology for early and accurate test power estimation at RTL. ITC Abhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe
2009	J	`jnl`	Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. J. Low Power Electron. George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi
2008	Misc	`conf`	A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. VTS Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji
2008	J	`jnl`	Low Power Test for Nanometer System-on-Chips (SoCs). J. Low Power Electron. Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena
2008	—	`conf`	Power Analysis and Reduction Techniques for Transition Fault Testing. ATS Khushboo Agarwal, Srinivas Vooka, Srivaths Ravi, Rubin A. Parekhji, Arjun Singh Gill
2008	J	`jnl`	Systematic Software-Based Self-Test for Pipelined Processors. IEEE Trans. Very Large Scale Integr. Syst. Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
2008	Misc	`conf`	Variability-Tolerant Register-Transfer Level Synthesis. VLSI Design Anish Muttreja, Srivaths Ravi, Niraj K. Jha
2007	J	`jnl`	A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. IEEE Trans. Very Large Scale Integr. Syst. Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
2007	J	`jnl`	Architectural Support for Run-Time Validation of Program Data Properties. IEEE Trans. Very Large Scale Integr. Syst. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	Automated Energy/Performance Macromodeling of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007	J	`jnl`	Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. IEEE Trans. Very Large Scale Integr. Syst. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
2007	A	`conf`	Energy and execution time analysis of a software-based trusted platform module. DATE Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007	J	`jnl`	Energy-optimizing source code transformations for operating system-driven embedded software. ACM Trans. Embed. Comput. Syst. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. Very Large Scale Integr. Syst. Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
2007	J	`jnl`	Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	Hardware Accelerated Power Estimation CoRR Joel Coburn, Srivaths Ravi, Anand Raghunathan
2007	J	`jnl`	Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2007	J	`jnl`	Hybrid Simulation for Energy Estimation of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2007	A	`conf`	Methodology for low power test pattern generation using activity threshold control logic. ICCAD Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji
2007	A	`conf`	Power-aware test: Challenges and solutions. ITC Srivaths Ravi
2007	Misc	`conf`	Tutorial T1: Designing Secure SoCs. VLSI Design Srivaths Ravi, Stefan Mangard
2006	J	`jnl`	A Scalable Synthesis Methodology for Application-Specific Processors. IEEE Trans. Very Large Scale Integr. Syst. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	J	`jnl`	A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. IEEE Trans. Mob. Comput. Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	C	`conf`	Active Learning Driven Data Acquisition for Sensor Networks. ISCC Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2006	J	`jnl`	Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	Misc	`conf`	Architectural support for safe software execution on embedded processors. CODES+ISSS Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2006	—	`conf`	Architectures for efficient face authentication in embedded systems. DATE Designers' Forum Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	J	`jnl`	Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	Misc	`conf`	Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. VLSI Design Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	Misc	`conf`	Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. VLSI Design Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
2006	J	`jnl`	RTL-Aware Cycle-Accurate Functional Power Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2006	—	`conf`	Safe Java Native Interface. ISSSE Gang Tan, Andrew W. Appel, Srimat Chakradhar, Anand Raghunathan, Srivaths Ravi, Daniel C. Wang
2006	—	`conf`	Satisfiability-based framework for enabling side-channel attacks on cryptographic software. DATE Designers' Forum Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
2006	J	`jnl`	Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
2006	A*	`conf`	Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
2006	A*	`conf`	Systematic software-based self-test for pipelined processors. DAC Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
2006	J	`jnl`	Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
2006	J	`jnl`	Use of Computation-Unit Integrated Memories in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	A*	`conf`	Efficient fingerprint-based user authentication for embedded systems. DAC Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	—	`conf`	Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory. CICC Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	Misc	`conf`	Enhancing security through hardware-assisted run-time validation of program data properties. CODES+ISSS Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2005	J	`jnl`	Generation of distributed logic-memory architectures through high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	A	`conf`	Hardware Accelerated Power Estimation. DATE Joel Coburn, Srivaths Ravi, Anand Raghunathan
2005	Misc	`conf`	Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
2005	A*	`conf`	Hybrid simulation for embedded software energy estimation. DAC Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2005	A*	`conf`	Power emulation: a new paradigm for power estimation. DAC Joel Coburn, Srivaths Ravi, Anand Raghunathan
2005	Misc	`conf`	SECA: security-enhanced communication architecture. CASES Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2005	A	`conf`	Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. DATE Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2005	Misc	`conf`	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. VLSI Design Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	J	`jnl`	A hybrid energy-estimation technique for extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	A*	`conf`	Automated energy/performance macromodeling of embedded software. DAC Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
2004	J	`jnl`	Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	Misc	`conf`	Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. VLSI Design Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	A	`conf`	High-level synthesis using computation-unit integrated memories. ICCAD Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	A	`conf`	Power estimation for cycle-accurate functional descriptions of hardware. ICCAD Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2004	A*	`conf`	Security as a new dimension in embedded system design. DAC Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan
2004	J	`jnl`	Security in embedded systems: Design challenges. ACM Trans. Embed. Comput. Syst. Srivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady
2004	Misc	`conf`	Tamper Resistance Mechanisms for Secure, Embedded Systems. VLSI Design Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003	A	`conf`	A Scalable Application-Specific Processor Synthesis Methodology. ICCAD Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003	A*	`conf`	A scalable software-based self-test methodology for programmable processors. DAC Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey
2003	A	`conf`	Analyzing the energy consumption of security protocols. ISLPED Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003	Misc	`conf`	Efficient RTL Power Estimation for Large Designs. VLSI Design Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003	Misc	`conf`	Embedding Security in Wireless Embedded Systems. VLSI Design Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
2003	A	`conf`	Energy Estimation for Extensible Processors. DATE Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003	—	`conf`	On automatic generation of RTL validation test benches using circuit testing techniques. ACM Great Lakes Symposium on VLSI Indradeep Ghosh, Srivaths Ravi
2003	A	`conf`	Securing Mobile Appliances: New Challenges for the System Designer. DATE Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater
2003	A	`conf`	Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ICCAD Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2003	C	`conf`	Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ICCD Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
2003	A	`conf`	Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. DATE Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi
2002	—	`conf`	FLEXBAR: A crossbar switching fabric with improved performance and utilization. CICC Jacob Chang, Srivaths Ravi, Anand Raghunathan
2002	A	`conf`	High-level synthesis of distributed logic-memory architectures. ICCAD Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2002	J	`jnl`	High-level test compaction techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2002	—	`conf`	Optimizing public-key encryption for wireless clients. ICC Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
2002	—	`conf`	Securing Wireless Data: System Architecture Challenges. ISSS Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi
2002	—	`conf`	Special Session: Security on SoC. ISSS Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
2002	A	`conf`	Synthesis of custom processors based on extensible platforms. ICCAD Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
2002	A*	`conf`	System design methodologies for a wireless security processing platform. DAC Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass
2002	J	`jnl`	Test synthesis of systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Niraj K. Jha
2001	A	`conf`	Fast test generation for circuits with RTL and gate-level views. ITC Srivaths Ravi, Niraj K. Jha
2001	J	`jnl`	Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
2001	Misc	`conf`	Synthesis of System-on-a-chip for Testability. VLSI Design Srivaths Ravi, Niraj K. Jha
2001	J	`jnl`	TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. Very Large Scale Integr. Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2001	J	`jnl`	Testing of core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2001	A	`conf`	Transient Power Management Through High Level Synthesis. ICCAD Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
2000	A	`conf`	: Reducing test application time in high-level test generation. ITC Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
2000	C	`conf`	A Technique for Identifying RTL and Gate-Level Correspondences. ICCD Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
2000	Misc	`conf`	High-Level Synthesis with Variable-Latency Components. VLSI Design Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
2000	J	`jnl`	Integrating variable-latency components into high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana
2000	J	`jnl`	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1999	A	`conf`	A framework for testing core-based systems-on-a-chip. ICCAD Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1999	Misc	`conf`	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998	J	`jnl`	Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. J. Electron. Test. Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
1998	Misc	`conf`	Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. VLSI Design Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
1998	A	`conf`	Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. ICCAD Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
1998	A	`conf`	TAO: regular expression based high-level testability analysis and optimization. ITC Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha