Sriseshan Srikanth

17 papers A* 1Journal 5Unranked 10
YearRankTypeTitle / Venue / Authors
2024 — conf
Characterization and Design of 3D-Stacked Memory for Image Signal Processing on AR/VR Devices.
MEMSYS
Lita Yang, Changjung Kao, Sriseshan Srikanth, Huseyin Ekin Sumbul, Tony F. Wu, Huichu Liu, Edith Beigné
2024 — conf
SlimSLAM: An Adaptive Runtime for Visual-Inertial Simultaneous Localization and Mapping.
ASPLOS (3)
Armand Behroozi, Yuxiang Chen, Vlad Fruchter, Lavanya Subramanian, Sriseshan Srikanth, Scott A. Mahlke
2022 J jnl
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems.
IEEE Trans. Computers
Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
2021 J jnl
SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads.
ACM Trans. Archit. Code Optim.
Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
2020 — —
Energy efficient architectures for irregular data streams.
Sriseshan Srikanth
2020 — conf
Intrepydd: performance, productivity, and portability for data science application kernels.
Onward!
Tong Zhou, Jun Shirako, Anirudh Jain, Sriseshan Srikanth, Thomas M. Conte, Richard W. Vuduc, Vivek Sarkar
2020 J jnl
MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams.
ACM Trans. Archit. Code Optim.
Sriseshan Srikanth, Anirudh Jain, Joseph M. Lennon, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
2019 — conf
Experimental Insights from the Rogues Gallery.
ICRC
Jeffrey S. Young, E. Jason Riedy, Thomas M. Conte, Vivek Sarkar, Prasanth Chatarasi, Sriseshan Srikanth
2018 J jnl
Extending Moore's Law via Computationally Error-Tolerant Computing.
ACM Trans. Archit. Code Optim.
Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
2018 A* conf
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures.
HPCA
Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank
2018 — conf
Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip.
ICRC
Anirudh Jain, Sriseshan Srikanth, Erik P. DeBenedictis, Tushar Krishna
2018 — conf
Tackling memory access latency through DRAM row management.
MEMSYS
Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang
2017 — conf
Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C.
HPEC
Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte
2017 — conf
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing.
ICRC
Sriseshan Srikanth, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook
2016 J jnl
A Brief Survey of Non-Residue Based Computational Error Correction.
CoRR
Sriseshan Srikanth, Bobin Deng, Thomas M. Conte
2016 — conf
Computationally-redundant energy-efficient processing for y'all (CREEPY).
ICRC
Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook
2016 — conf
Energy efficiency limits of logic and memory.
ICRC
Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte