Srinivas Patil

31 papers A* 2A 8C 1Misc 3Journal 9Unranked 7
YearRankTypeTitle / Venue / Authors
2012 J jnl
Functional Test-Sequence Grading at Register-Transfer Level.
IEEE Trans. Very Large Scale Integr. Syst.
Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti
2012 A conf
Test generation for clock-domain crossing faults in integrated circuits.
DATE
Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil
2011 — conf
Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip.
Asian Test Symposium
Naghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil
2009 J jnl
FPGA-based hardware acceleration for Boolean satisfiability.
ACM Trans. Design Autom. Electr. Syst.
Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas
2009 Misc conf
RT-Level Deviation-Based Grading of Functional Test Sequences.
VTS
Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti
2009 J jnl
The Challenges of Nanotechnology and Gigacomplexity.
IEEE Des. Test Comput.
Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp
2008 A conf
A low-cost concurrent error detection technique for processor control logic.
DATE
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche
2007 — conf
Analysis of Specified Bit Handling Capability of Combinational Expander Networks.
DFT
Abhijit Jas, Srinivas Patil
2007 — conf
Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation.
ATS
Irith Pomeranz, Praveen Parvathala, Srinivas Patil
2007 — conf
The Region-Exhaustive Fault Model.
ATS
Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil
2006 A conf
A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests.
ITC
Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz
2006 — conf
A Functional Fault Model with Implicit Fault Effect Propagation Requirements.
ATS
Irith Pomeranz, Srinivas Patil, Praveen Parvathala
2006 Misc conf
Path Delay Fault Simulation on Large Industrial Designs.
VTS
Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty
2006 — conf
Selecting High-Quality Delay Tests for Manufacturing Test and Debug.
DFT
Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz
2005 — conf
Compressing Functional Tests for Microprocessors.
Asian Test Symposium
Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil
1996 J jnl
A weighted random pattern test generation system.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
1994 J jnl
Broad-side delay test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jacob Savir, Srinivas Patil
1994 A conf
Design of an Efficient Weighted-Random-Pattern Generation System.
ITC
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
1994 Misc conf
On broad-side delay test.
VTS
Jacob Savir, Srinivas Patil
1994 J jnl
On broad-side delay test.
IEEE Trans. Very Large Scale Integr. Syst.
Jacob Savir, Srinivas Patil
1993 J jnl
Scan-based transition test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jacob Savir, Srinivas Patil
1992 A conf
Skewed-Load Transition Test: Part 2, Coverage.
ITC
Srinivas Patil, Jacob Savir
1991 A conf
A Layout Driven Design for Testability Technique for MOS VLSI Circuits.
ITC
Sungho Kim, Prithviraj Banerjee, Srinivas Patil
1991 A* conf
Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors.
DAC
Srinivas Patil, Prithviraj Banerjee, Janak H. Patel
1991 — —
Parallel algorithms for test generation and fault simulation
Srinivas Patil
1991 J jnl
Performance trade-offs in a parallel test generation/fault simulation environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Srinivas Patil, Prithviraj Banerjee
1990 J jnl
A parallel branch and bound algorithm for test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Srinivas Patil, Prithviraj Banerjee
1989 A* conf
A Parallel Branch and Bound Algorithm for Test Generation.
DAC
Srinivas Patil, Prithviraj Banerjee
1989 C conf
A test generation system for path delay faults.
ICCD
Srinivas Patil, Sudhakar M. Reddy
1989 A conf
Efficient circuit partitioning algorithms for parallel logic simulation.
SC
Srinivas Patil, Prithviraj Banerjee, Constantine D. Polychronopoulos
1989 A conf
Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment.
ITC
Srinivas Patil, Prithviraj Banerjee