Srinivas Boppu

31 papers A 1C 2Misc 1Journal 11Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	In-Memory Computing Architecture for Tsetlin Machine Inference using MTJ-based Crossbar. ISCAS Akash Kumar, Vineeth Botsa, Omar Ghazal, Srinivas Boppu, Rishad Shafik
2025	J	`jnl`	Quality-Aware PPG-Based Blood Pressure Classification for Energy-Efficient Trustworthy BP Monitoring Devices With Reduced False Alarms. IEEE Access Yalagala Sivanjaneyulu, M. Sabarimalai Manikandan, Srinivas Boppu, Linga Reddy Cenkeramaddi
2025	J	`jnl`	SteganoSNN: SNN-Based Audio-in-Image Steganography with Encryption. CoRR Biswajit Kumar Sahoo, Pedro Machado, Isibor Kennedy Ihianle, Andreas Oikonomou, Srinivas Boppu
2024	J	`jnl`	Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study. IEEE Access Pudi Dhilleswararao, Yu Yang, Dimitrios Stathis, Sunil Kumar Prajapati, Srinivas Boppu, Ahmed Hemani, Linga Reddy Cenkeramaddi
2024	J	`jnl`	Automating functional unit and register binding for synchoros CGRA platform. Des. Autom. Embed. Syst. Pudi Dhilleswararao, Utsav Tiwari, Srinivas Boppu, Yu Yang, Ahmed Hemani
2024	J	`jnl`	Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework. IEEE Access Pudi Dhilleswararao, Shivam Malviya, Srinivas Boppu, Yu Yang, Ahmed Hemani, Linga Reddy Cenkeramaddi
2024	J	`jnl`	Resource-Efficient Derivative PPG-Based Signal Quality Assessment Using One-Dimensional CNN With Optimal Hyperparameters for Quality-Aware PPG Analysis. IEEE Access Yalagala Sivanjaneyulu, M. Sabarimalai Manikandan, Srinivas Boppu, Linga Reddy Cenkeramaddi
2023	A	`conf`	Compressive Sensing-Based Automatic PPG Signal Quality Assessment Using CNN for Energy-Constrained Medical Devices. ECAI Yalagala Sivanjaneyulu, Srinivas Boppu, M. Sabarimalai Manikandan
2023	Misc	`conf`	DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. VLSID Reeshita Kallapu, Dimitrios Stathis, Srinivas Boppu, Ahmed Hemani
2023	J	`jnl`	Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction. ACM Trans. Design Autom. Electr. Syst. Ashish Reddy Bommana, Susheel Ujwal Siddamshetty, Pudi Dhilleswararao, Arvind Thumatti K. R., Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi
2023	—	`conf`	Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. HEART Pudi Dhilleswararao, Rajeev Ryansh, Srinivas Boppu, Yu Yang, Ahmed Hemani
2023	—	`conf`	Implementation of Image Averaging on DRRA and DiMArch Architectures. SBCCI Pudi Dhilleswararao, Vamsi Goudu, Srinivas Boppu, Ritika Ratnu, Ahmed Hemani
2023	C	`conf`	Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures. DSD Pudi Dhilleswararao, Rajeev Ryansh, Vamsi Goudu, Srinivas Boppu, Ahmed Hemani
2022	—	`conf`	A Run-time Tapered Floating-Point Adder/Subtractor Supporting Vectorization. MCSoC Ashish Reddy Bommana, Srinivas Boppu
2022	—	`conf`	Efficient Hardware Architecture for Posit Addition/Subtraction. MCSoC Susheel Ujwal Siddamshetty, Srinivas Boppu, Debapratim Ghosh
2022	J	`jnl`	Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey. IEEE Access Pudi Dhilleswararao, Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi
2022	—	`conf`	Efficient Multiplication and Accumulation of Signed Numbers. iSES Susheel Ujwal Siddamshetty, Suresh Nambi, Srinivas Boppu, Debapratim Ghosh
2022	—	`conf`	Hand Gesture Recognition System in the Complex Background for Edge Computing Devices. iSES Chakkapalli Manikanta Suryateja, Srinivas Boppu, Linga Reddy Cenkeramaddi, Barathram Ramkumar
2021	—	`conf`	Design and Implementation of Optimized Register File for Streaming Applications. VDAT Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani
2020	—	`conf`	An Automated Algorithm for Estimating Respiration Rate from PPG Signals. MIND (2) Kinjarapu Manojkumar, Srinivas Boppu, M. Sabarimalai Manikandan
2020	—	`conf`	Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats. VDAT Arvind Thumatti K. R., Marcel Brand, Christian Heidorn, Srinivas Boppu, Frank Hannig, Jürgen Teich
2019	—	`conf`	Design of a Real-Time Automatic Source Monitoring Framework Based on Sound Source Localization. ICDIPC Spandan Dey, Srinivas Boppu, M. Sabarimalai Manikandan
2015	—	`—`	Code Generation for Tightly Coupled Processor Arrays. Srinivas Boppu
2014	J	`jnl`	Compact Code Generation for Tightly-Coupled Processor Arrays. J. Signal Process. Syst. Srinivas Boppu, Frank Hannig, Jürgen Teich
2014	J	`jnl`	Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach. ACM Trans. Embed. Comput. Syst. Frank Hannig, Vahid Lari, Srinivas Boppu, Alexandru Tanase, Oliver Reiche
2013	—	`conf`	Loop program mapping and compact code generation for programmable hardware accelerators. ASAP Srinivas Boppu, Frank Hannig, Jürgen Teich
2013	—	`conf`	System integration of tightly-coupled processor arrays using reconfigurable buffer structures. Conf. Computing Frontiers Frank Hannig, Moritz Schmid, Vahid Lari, Srinivas Boppu, Jürgen Teich
2012	—	`conf`	A prototype of an invasive tightly-coupled processor array. DASIP Shravan Muddasani, Srinivas Boppu, Frank Hannig, Boris Kuzmin, Vahid Lari, Jürgen Teich
2012	—	`conf`	Design of Low Power On-chip Processor Arrays. ASAP Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Jürgen Teich
2012	J	`jnl`	Hierarchical power management for adaptive tightly-coupled processor arrays. ACM Trans. Design Autom. Electr. Syst. Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmid, Jürgen Teich
2011	—	`conf`	Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. ReConFig Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade