Srinath R. Naidu

12 papers A* 1A 2Misc 2Journal 3Unranked 4
YearRankTypeTitle / Venue / Authors
2024 J jnl
Optimal oversampling ratio in two-step simulation.
Monte Carlo Methods Appl.
Srinath R. Naidu, Gopalakrishnan Venkiteswaran
2018 — conf
Fast Approach for Iris Detection on GPU by Applying Search Localization for Circular Hough Transform.
ICACCI
Pinkey Kumari, Srinath R. Naidu
2016 — conf
Accelerated evolutionary algorithms with parameterimportance based population initialization for variation-aware analog yield optimization.
MWSCAS
Sita Kondamadugula, Srinath R. Naidu
2016 — conf
Parameter-importance based Monte-Carlo Technique for Variation-aware Analog Yield Optimization.
ACM Great Lakes Symposium on VLSI
Sita Kondamadugula, Srinath R. Naidu
2015 Misc conf
Geometric Programming Formulation for Gate Sizing with Pipelining Constraints.
VLSID
Srinath R. Naidu
2007 Misc conf
Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits.
VLSI Design
Srinath R. Naidu
2007 A conf
Use of statistical timing analysis on real designs.
DATE
A. Nardi, Emre Tuncer, Srinath R. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song
2006 J jnl
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
2003 J jnl
On Synthesis of Easily Testable (k, K) Circuits.
IEEE Trans. Computers
Srinath R. Naidu, Vijay Chandru
2003 A* conf
Statistical timing for parametric yield prediction of digital integrated circuits.
DAC
Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
2002 — conf
Timing Yield Calculation Using an Impulse-Train Approach.
ASP-DAC/VLSI Design
Srinath R. Naidu
2001 A conf
Minimizing stand-by leakage power in static CMOS circuits.
DATE
Srinath R. Naidu, E. T. A. F. Jacobs