Srilata Raman

12 papers A* 1B 1Journal 8Unranked 2
YearRankTypeTitle / Venue / Authors
1997 A* conf
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries.
DAC
Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernández, Larry G. Jones
1997 J jnl
Optimization Via Evolutionary Processes.
Adv. Comput.
Srilata Raman, Lalit M. Patnaik
1996 — conf
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs.
ED&TC
Srilata Raman, C. L. Liu, Larry G. Jones
1996 J jnl
Performance-driven MCM partitioning through an adaptive genetic algorithm.
IEEE Trans. Very Large Scale Integr. Syst.
Srilata Raman, Lalit M. Patnaik
1996 J jnl
Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation.
VLSI Design
Srilata Raman, C. L. Liu, Larry G. Jones
1995 J jnl
A genetic algorithm-based circuit partitioner for MCMs.
Microprocess. Microprogramming
Ananta K. Majhi, Lalit M. Patnaik, Srilata Raman
1994 J jnl
A Parallel Simulated Annealing-Based Channel Router.
Int. J. High Speed Comput.
Rajib Mall, Srilata Raman, Lalit M. Patnaik
1994 — conf
A delay driven FPGA placement algorithm.
EURO-DAC
Srilata Raman, C. L. Liu, Larry G. Jones
1991 B conf
Quality-time tradeoffs in simulated annealing for VLSI placement.
COMPSAC
Srilata Raman, Benjamin W. Wah
1990 J jnl
An Annealing-Based Circuit Partitioner for Hypercube Architecture: Design and Performance Evaluation.
Int. J. High Speed Comput.
Srilata Raman, Lalit M. Patnaik
1990 J jnl
Parallel Implementation of Circuit Simulation.
Int. J. High Speed Comput.
Srilata Raman, Lalit M. Patnaik, Rajib Mall
1989 J jnl
Hirecs: Hypercube Implementation of Relaxation-Based Circuit Simulation.
Int. J. High Speed Comput.
Srilata Raman, Lalit M. Patnaik