Srikanth Arekapudi

13 papers Journal 5Unranked 8
YearRankTypeTitle / Venue / Authors
2016 J jnl
Carrizo: A High Performance, Energy Efficient 28 nm APU.
IEEE J. Solid State Circuits
Benjamin Munger, David Akeson, Srikanth Arekapudi, Tom Burd, Harry R. Fair III, Jim Farrell, Dave Johnson, Guhan Krishnan, Hugh McIntyre, Edward McLellan, Samuel Naffziger, Russell Schreiber, Sriram Sundaram, Jonathan White, Kathryn Wilcox
2013 J jnl
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor.
IEEE J. Solid State Circuits
Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger
2012 J jnl
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS.
IEEE J. Solid State Circuits
Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy C. Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh
2012 — conf
Resonant clock design for a power-efficient high-volume x86-64 microprocessor.
ISSCC
Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger
2011 — conf
40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core.
ISSCC
Michael Golden, Srikanth Arekapudi, James Vinh
2011 — conf
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU.
ISSCC
Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox
2006 — conf
A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support.
ISSCC
Michael Golden, Srikanth Arekapudi, Greg Dabney, Mike Haertel, Stephen Hale, Lowell Herlinger, Yongg Kim, Kevin Mcgrath, Vasant Palisetti, Monica Singh
2005 — conf
A low-power distributed wide-band LNA in 0.18µm CMOS.
ISCAS (5)
Srikanth Arekapudi, Echere Iroaga, Boris Murmann
2005 J jnl
Using Hardware to Configure a Load-Balanced Switch.
IEEE Micro
Srikanth Arekapudi, Shang-Tse Chuang, Isaac Keslassy, Nick McKeown
2004 — conf
Configuring a load-balanced switch in hardware.
Hot Interconnects
Srikanth Arekapudi, Shang-Tse Chuang, Isaac Keslassy, Nick McKeown
2003 J jnl
ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems.
J. Circuits Syst. Comput.
Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris
2002 — conf
ATPG for timing-induced functional errors on trigger events in hardware-software systems.
ETW
Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris
2001 — conf
Test pattern generation for timing-induced functional errors in hardware-software systems.
HLDVT
Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris