Sri Parameswaran

233 papers A* 24A 39B 6C 13Misc 33Journal 63Unranked 50

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Scalable Network-on-Chip Design for FPGA Implementation. IEEE Access Mekala Bindu Bhargavi, Sai Siddharth Rokkam, Vattipelli Srinath, Sri Parameswaran, J. Soumya
2025	A*	`conf`	A Novel Covert Timing Channel for Cloud FPGAs. DAC Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran
2025	J	`jnl`	Approximate Multiplier Induced Error Propagation in Deep Neural Networks. CoRR A. M. H. H. Alahakoon, Hassaan Saadat, Darshana Jayasinghe, Sri Parameswaran
2025	—	`conf`	Cycle-Accurate ML-Based Power Modeling for RISC-V Cores Using RTL Simulations. SOCC Mekala Bindu Bhargavi, Rachakonda Komal Nayan, Sri Parameswaran, Soumya J.
2025	A	`conf`	JitFilt: Mitigate Jitter-based Side Channel Analysis Attacks. ICCAD Darshana Jayasinghe, Yuanhua Zhong, Sri Parameswaran
2025	J	`jnl`	Leveraging basecaller's move table to generate a lightweight k-mer model for nanopore sequencing analysis. Bioinform. Hiruna Samarakoon, Yuk Kei Wan, Sri Parameswaran, Jonathan Göke, Hasindu Gamaarachchi, Ira W. Deveson
2024	J	`jnl`	1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables. IACR Trans. Cryptogr. Hardw. Embed. Syst. Darshana Jayasinghe, Brian Udugama, Sri Parameswaran
2024	A	`conf`	Accelerating Chaining in Genomic Analysis Using RISC- V Custom Instructions. DATE Kisaru Liyanage, Hasindu Gamaarachchi, Hassaan Saadat, Tuo Li, Hiruna Samarakoon, Sri Parameswaran
2024	—	`conf`	Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA. VDAT Mekala Bindu Bhargavi, Sai Siddharth Rokkam, Sri Parameswaran, Soumya J.
2024	J	`jnl`	Interactive visualization of nanopore sequencing signal data with Bioinform. Hiruna Samarakoon, Kisaru Liyanage, James M. Ferguson, Sri Parameswaran, Hasindu Gamaarachchi, Ira W. Deveson
2024	J	`jnl`	MP-ORAM: A Novel ORAM Design for Multicore Processor Systems. IEEE Trans. Dependable Secur. Comput. Sajid Hussain, Hui Guo, Tuo Li, Sri Parameswaran
2024	C	`conf`	Optimizing Convolutional Image Processing on RISC-V Using Branch Prediction on FPGA. TENCON Mekala Bindu Bhargavi, Sujay Krishnan Subramanian, Sri Parameswaran, Soumya J.
2024	—	`conf`	Optimizing LU Decomposition with RISC-V Based Hardware Acceleration. ISVLSI Mekala Bindu Bhargavi, Grandhala Sri Sai Harshith, Sri Parameswaran, Soumya J.
2024	J	`jnl`	Physical and Software Based Fault Injection Attacks Against TEEs in Mobile Devices: A Systemisation of Knowledge. CoRR Aaron Joy, Ben Soh, Zhi Zhang, Sri Parameswaran, Darshana Jayasinghe
2024	A	`conf`	SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators. DATE Jing Gong, Hassaan Saadat, Haris Javaid, Hasindu Gamaarachchi, David Taubman, Sri Parameswaran
2024	—	`ed.`	Security, Privacy, and Applied Cryptography Engineering - 13th International Conference, SPACE 2023, Roorkee, India, December 14-17, 2023, Proceedings SPACE Francesco Regazzoni, Bodhisatwa Mazumdar, Sri Parameswaran
2024	B	`conf`	Sensors for Remote Power Attacks: New Developments and Challenges. ASPDAC Brian Udugama, Darshana Jayasinghe, Sri Parameswaran
2023	J	`jnl`	ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jing Gong, Hassaan Saadat, Hasindu Gamaarachchi, Haris Javaid, Xiaobo Sharon Hu, Sri Parameswaran
2023	J	`jnl`	Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kisaru Liyanage, Hasindu Gamaarachchi, Roshan G. Ragel, Sri Parameswaran
2023	—	`conf`	FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers. ASP-DAC Darshana Jayasinghe, Brian Udugama, Sri Parameswaran
2023	A*	`conf`	Invited: Algorithms and Architectures for Accelerating Long Read Sequence Analysis. DAC Hasindu Gamaarachchi, Kisaru Liyanage, Sri Parameswaran
2023	J	`jnl`	Special Issue: "Approximation at the Edge". ACM Trans. Embed. Comput. Syst. Alberto Bosio, Lara Dolecek, Alexandra Kourfali, Sri Parameswaran, Alessandro Savino
2022	J	`jnl`	A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran
2022	J	`jnl`	ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference. CoRR Jing Gong, Hassaan Saadat, Hasindu Gamaarachchi, Haris Javaid, Xiaobo Sharon Hu, Sri Parameswaran
2022	J	`jnl`	Efficient Real-Time Selective Genome Sequencing on Resource-Constrained Devices. CoRR Po Jui Shih, Hassaan Saadat, Sri Parameswaran, Hasindu Gamaarachchi
2022	A*	`conf`	FaSe: fast selective flushing to mitigate contention-based cache timing attacks. DAC Tuo Li, Sri Parameswaran
2022	J	`jnl`	Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks. CoRR Tuo Li, Sri Parameswaran
2022	A*	`conf`	HWST128: complete memory safety accelerator on RISC-V with metadata compression. DAC Hsu-Kang Dow, Tuo Li, Sri Parameswaran
2022	J	`jnl`	VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs. IACR Trans. Cryptogr. Hardw. Embed. Syst. Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran
2021	—	`conf`	Approximate Computing for ML: State-of-the-art, Challenges and Visions. ASP-DAC Georgios Zervakis, Hassaan Saadat, Hussam Amrouch, Andreas Gerstlauer, Sri Parameswaran, Jörg Henkel
2021	J	`jnl`	COPS: A complete oblivious processing system. Microprocess. Microsystems Sajid Hussain, Hui Guo, Tuo Li, Hassaan Saadat, Sri Parameswaran
2021	J	`jnl`	QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks. ACM Trans. Design Autom. Electr. Syst. Darshana Jayasinghe, Aleksandar Ignjatovic, Roshan G. Ragel, Jude Angelo Ambrose, Sri Parameswaran
2021	A*	`conf`	SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V. DAC Hsu-Kang Dow, Tuo Li, William Miles, Sri Parameswaran
2021	J	`jnl`	UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks. IEEE Access Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
2020	Misc	`conf`	A Sub-Range Error Characterization based Selection Methodology for Approximate Arithmetic Units. VLSID Hassaan Saadat, Tuo Li, Haris Javaid, Sri Parameswaran
2020	J	`jnl`	Cache Friendly Optimisation of de Bruijn Graph Based Local Re-Assembly in Variant Calling. IEEE ACM Trans. Comput. Biol. Bioinform. Hasindu Gamaarachchi, Arash Bayat, Bruno Gaëta, Sri Parameswaran
2020	J	`jnl`	FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vikkitharan Gnanasambandapillai, Jorgen Peddersen, Roshan G. Ragel, Sri Parameswaran
2020	J	`jnl`	Fast Short Read De-Novo Assembly Using Overlap-Layout-Consensus Approach. IEEE ACM Trans. Comput. Biol. Bioinform. Arash Bayat, Nandan P. Deshpande, Marc R. Wilkins, Sri Parameswaran
2020	J	`jnl`	GPU accelerated adaptive banded event alignment for rapid comparative nanopore signal analysis. BMC Bioinform. Hasindu Gamaarachchi, Wai Chun Lam, Gihan Jayatilaka, Hiruna Samarakoon, Jared T. Simpson, Martin A. Smith, Sri Parameswaran
2020	J	`jnl`	Hardware Trojan Mitigation in Pipelined MPSoCs. ACM Trans. Design Autom. Electr. Syst. Amin Malekpour, Roshan G. Ragel, Tuo Li, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2020	B	`conf`	LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs. FPL Farah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran
2020	A	`conf`	REALM: Reduced-Error Approximate Log-based Integer Multiplier. DATE Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2020	J	`jnl`	SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation. CoRR Tuo Li, Bradley Hopkins, Sri Parameswaran
2020	A	`conf`	Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping. ICCAD Ann Franchesca Laguna, Hasindu Gamaarachchi, Xunzhao Yin, Michael T. Niemier, Sri Parameswaran, Xiaobo Sharon Hu
2020	—	`conf`	WEID: Worst-case Error Improvement in Approximate Dividers. ASP-DAC Hassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2019	A*	`conf`	Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias. DAC Hassaan Saadat, Haris Javaid, Sri Parameswaran
2019	C	`conf`	Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing. DDECS Amin Malekpour, Roshan G. Ragel, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran
2019	J	`jnl`	Pairwise alignment of nucleotide sequences using maximal exact matches. BMC Bioinform. Arash Bayat, Bruno Gaëta, Aleksandar Ignjatovic, Sri Parameswaran
2019	A*	`conf`	RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis Attacks. DAC Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
2019	A	`conf`	SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks. ICCAD Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
2019	J	`jnl`	SWARAM: Portable Energy and Cost Efficient Embedded System for Genomic Processing. ACM Trans. Embed. Comput. Syst. Ram Prasad Mohanty, Hasindu Gamaarachchi, Andrew J. Lambert, Sri Parameswaran
2018	J	`jnl`	Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). IEEE Des. Test Sri Parameswaran, R. Iris Bahar, David Z. Pan
2018	—	`conf`	CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support. ASP-DAC Florencia Irena, Daniel Murphy, Sri Parameswaran
2018	—	`conf`	EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection in Untrusted Network-on-Chip. ISVLSI Mubashir Hussain, Amin Malekpour, Hui Guo, Sri Parameswaran
2018	—	`conf`	MESGA: An MPSoC based embedded system solution for short read genome alignment. ASP-DAC Vikkitharan Gnanasambandapillai, Arash Bayat, Sri Parameswaran
2018	J	`jnl`	Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hassaan Saadat, Haseeb Bokhari, Sri Parameswaran
2017	A	`ed.`	2017 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2017, Irvine, CA, USA, November 13-16, 2017 ICCAD Sri Parameswaran
2017	—	`conf`	DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks. ASAP Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran
2017	J	`jnl`	Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors. IEEE Trans. Computers Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
2017	Misc	`conf`	Hardware approximate computing: how, why, when and where? (special session). CASES Hassaan Saadat, Sri Parameswaran
2017	J	`jnl`	Improved VCF normalization for accurate VCF comparison. Bioinform. Arash Bayat, Bruno Gaëta, Aleksandar Ignjatovic, Sri Parameswaran
2017	Misc	`conf`	NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks. VLSID Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran
2017	—	`ch.`	Network-on-Chip Design. Handbook of Hardware/Software Codesign Haseeb Bokhari, Sri Parameswaran
2017	J	`jnl`	Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran
2017	—	`conf`	Social Presence in Social Media: Persuasion, Design and Discourse. SIGMIS-CPR Sri Parameswaran
2017	A*	`conf`	TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs. DAC Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran
2017	J	`jnl`	iCETD: An improved tag generation design for memory data authentication in embedded processor systems. Integr. Tao Liu, Hui Guo, Sri Parameswaran, Xiaobo Sharon Hu
2016	J	`jnl`	Dark Silicon: From Embedded to HPC Systems (Dagstuhl Seminar 16052). Dagstuhl Reports Hans Michael Gerndt, Michael Glaß, Sri Parameswaran, Barry L. Rountree
2016	—	`conf`	Does it sound as it claims: a detailed side-channel security analysis of QuadSeal countermeasure. Conf. Computing Frontiers Darshana Jayasinghe, Shivam Bhasin, Sri Parameswaran, Aleksandar Ignjatovic
2016	J	`jnl`	Editorial Introduction of New Editor-in-Chief and Associate Editors. IEEE Embed. Syst. Lett. Sri Parameswaran
2016	—	`conf`	Improving tag generation for memory data authentication in embedded processor systems. ASP-DAC Tao Liu, Hui Guo, Sri Parameswaran, Xiaobo Sharon Hu
2016	J	`jnl`	Processor Design for Soft Errors: Challenges and State of the Art. ACM Comput. Surv. Tuo Li, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
2016	A	`conf`	RECORD: Reducing register traffic for checkpointing in embedded processors. DATE Tuo Li, Jude Angelo Ambrose, Sri Parameswaran
2016	—	`conf`	Self-timed automatic test pattern generation for null convention logic. MWSCAS Nastaran Nemati, Mark C. Reed, Sri Parameswaran, Karl M. Fant
2016	J	`jnl`	Switchable cache: utilising dark silicon for application specific cache optimisations. IET Comput. Digit. Tech. Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Sri Parameswaran
2016	C	`conf`	The effect of amplitude resolution and mismatch on a digital-to-analog converter used for digital harmonic-cancelling sine-wave synthesis. ISCAS Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran
2015	—	`conf`	ADAPT: An adaptive manycore methodology for software pipelined applications. ASP-DAC Xi Zhang, Haris Javaid, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
2015	C	`conf`	ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip. ISCAS Jude Angelo Ambrose, Nick Higgins, Mrinal Chakravarthy, Shivam Gargg, Tuo Li, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran
2015	Misc	`conf`	ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA. VLSID Jude Angelo Ambrose, Tuo Li, Daniel Murphy, Shivam Gargg, Nick Higgins, Sri Parameswaran
2015	J	`jnl`	CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique. CoRR Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
2015	J	`jnl`	DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy. CoRR Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2015	—	`conf`	Dark Silicon: From Computation to Communication. NOCS Jörg Henkel, Haseeb Bokhari, Siddharth Garg, Muhammad Usman Karim Khan, Heba Khdr, Florian Kriebel, Ümit Y. Ogras, Sri Parameswaran, Muhammad Shafique
2015	C	`conf`	Design of a digital harmonic-cancelling sine-wave synthesizer with 100 MHz output frequency, 43.5 dB SFDR, and 2.26 mW power. ISCAS Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran
2015	A	`conf`	Dynamic reconfigurable puncturing for secure wireless communication. DATE Liang Tang, Jude Angelo Ambrose, Akash Kumar, Sri Parameswaran
2015	A	`conf`	E-pipeline: elastic hardware/software pipelines on a many-core fabric. DATE Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jörg Henkel, Sri Parameswaran
2015	J	`jnl`	Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran
2015	A	`conf`	Malleable NoC: dark silicon inspired adaptable Network-on-Chip. DATE Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2015	Misc	`conf`	QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks. CASES Darshana Jayasinghe, Aleksandar Ignjatovic, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
2015	C	`conf`	RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. ICCD Su Myat Min Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen, Sri Parameswaran
2015	J	`jnl`	SecureD: A Secure Dual Core Embedded Processor. CoRR Roshan G. Ragel, Jude Angelo Ambrose, Sri Parameswaran
2015	C	`conf`	Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. ICCD Jude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran
2015	—	`conf`	Side channel attacks in embedded systems: A tale of hostilities and deterrence. ISQED Jude Angelo Ambrose, Roshan G. Ragel, Darshana Jayasinghe, Tuo Li, Sri Parameswaran
2015	—	`conf`	Speeding up single pass simulation of PLRUt caches. ASP-DAC Josef Schneider, Jorgen Peddersen, Sri Parameswaran
2015	A*	`conf`	SuperNet: multimode interconnect architecture for manycore chips. DAC Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2014	—	`conf`	A scorchingly fast FPGA-based Precise L1 LRU cache simulator. ASP-DAC Josef Schneider, Jorgen Peddersen, Sri Parameswaran
2014	C	`conf`	A simple digital architecture for a harmonic-cancelling sine-wave synthesizer. ISCAS Pasindu Aluthwala, Neil Weste, Andrew Adams, Torsten Lehmann, Sri Parameswaran
2014	C	`conf`	Advanced modes in AES: Are they safe from power analysis based side channel attacks? ICCD Darshana Jayasinghe, Roshan G. Ragel, Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran
2014	Misc	`conf`	Dark silicon as a challenge for hardware/software co-design. CODES+ISSS Muhammad Shafique, Siddharth Garg, Tulika Mitra, Sri Parameswaran, Jörg Henkel
2014	J	`jnl`	Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2014	A*	`conf`	FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs. DAC Haris Javaid, Yusuke Yachide, Su Myat Min Shwe, Haseeb Bokhari, Sri Parameswaran
2014	A	`conf`	Flexible and scalable implementation of H.264/AVC encoder for multiple resolutions using ASIPs. DATE Hong Chinh Doan, Haris Javaid, Sri Parameswaran
2014	A	`conf`	Hardware-based fast exploration of cache hierarchies in application specific MPSoCs. DATE Isuru Nawinne, Josef Schneider, Haris Javaid, Sri Parameswaran
2014	A*	`conf`	MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis. DAC Josef Schneider, Jorgen Peddersen, Sri Parameswaran
2014	—	`conf`	Mapping programs for execution on pipelined MPSoCs. ESTIMedia Sri Parameswaran
2014	J	`jnl`	Performance Estimation of Pipelined MultiProcessor System-on-Chips (MPSoCs). IEEE Trans. Parallel Distributed Syst. Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2014	—	`book`	Pipelined Multiprocessor System-on-Chip for Multimedia. Haris Javaid, Sri Parameswaran
2014	—	`conf`	Reconfigurable Convolutional Codec for Physical Layer Communication Security Application. MILCOM Liang Tang, Jude Angelo Ambrose, Sri Parameswaran, Sha Zhu
2014	—	`conf`	SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. ASP-DAC Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide
2014	A*	`conf`	darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon. DAC Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2013	Misc	`conf`	A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. VLSI Design Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran
2013	—	`conf`	A case study on exploration of last-level cache for energy reduction in DDR3 DRAM. MECO Su Myat Min, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2013	—	`conf`	A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES. ISVLSI Ankita Arora, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
2013	—	`conf`	A novel intermittent fault Markov model for deep sub-micron processors. ACM Great Lakes Symposium on VLSI Babak Saghaie, Roshan G. Ragel, Sri Parameswaran, Aleksandar Ignjatovic
2013	A	`conf`	An extremely compact JPEG encoder for adaptive embedded systems. DATE Josef Schneider, Sri Parameswaran
2013	A	`conf`	CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. DATE Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
2013	A	`conf`	DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems. ICCAD Tuo Li, Muhammad Shafique, Semeen Rehman, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran
2013	—	`conf`	DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja
2013	—	`conf`	Dynamic encryption key design and management for memory data encryption in embedded systems. ISVLSI Mei Hong, Hui Guo, Sri Parameswaran
2013	C	`conf`	Energy-aware synthesis of application specific MPSoCs. ICCD Thannirmalai Somu Muthukaruppan, Haris Javaid, Tulika Mitra, Sri Parameswaran
2013	C	`conf`	Latency-constrained binding of data flow graphs to energy conscious GALS-based MPSoCs. ISCAS Jude Angelo Ambrose, Isuru Nawinne, Sri Parameswaran
2013	Misc	`conf`	MAPro: A Tiny Processor for Reconfigurable Baseband Modulation Mapping. VLSI Design Liang Tang, Jude Angelo Ambrose, Sri Parameswaran
2013	—	`conf`	Multi-mode pipelined MPSoCs for streaming applications. ASP-DAC Haris Javaid, Daniel Witono, Sri Parameswaran
2013	A*	`conf`	RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors. DAC Tuo Li, Muhammad Shafique, Jude Angelo Ambrose, Semeen Rehman, Jörg Henkel, Sri Parameswaran
2013	—	`conf`	RExCache: Rapid exploration of unified last-level cache. ASP-DAC Su Myat Min, Haris Javaid, Sri Parameswaran
2013	A*	`conf`	Reconfigurable pipelined coprocessor for multi-mode communication transmission. DAC Liang Tang, Jude Angelo Ambrose, Sri Parameswaran
2013	Misc	`conf`	Run-time adaption for highly-complex multi-core systems. CODES+ISSS Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Jürgen Teich
2013	—	`conf`	System-level optimization of on-chip communication using express links for throughput constrained MPSoCs. ESTIMedia Haseeb Bokhari, Haris Javaid, Sri Parameswaran
2013	C	`conf`	Variable increment step based reconfigurable interleaver for multimode communication application. ISCAS Liang Tang, Jude Angelo Ambrose, Sri Parameswaran
2013	A*	`conf`	XDRA: exploration and optimization of last-level cache for energy reduction in DDR DRAMs. DAC Su Myat Min, Haris Javaid, Sri Parameswaran
2012	Misc	`conf`	A Rapid Methodology for Multi-mode Communication Circuit Generation. VLSI Design Liang Tang, Jorgen Peddersen, Sri Parameswaran
2012	C	`conf`	CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study. ISCAS Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran
2012	Misc	`conf`	DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. CODES+ISSS Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran
2012	A	`conf`	Fine-grained hardware/software methodology for process migration in MPSoCs. ICCAD Tuo Li, Jude Angelo Ambrose, Sri Parameswaran
2012	J	`jnl`	Randomized Instruction Injection to Counter Power Analysis Attacks. ACM Trans. Embed. Comput. Syst. Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
2012	A	`conf`	Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors. DATE Tuo Li, Roshan G. Ragel, Sri Parameswaran
2011	B	`conf`	A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks. TrustCom Ankita Arora, Sri Parameswaran, Roshan G. Ragel, Darshana Jayasinghe
2011	J	`jnl`	A hybrid hardware-software technique to improve reliability in embedded processors. ACM Trans. Embed. Comput. Syst. Roshan G. Ragel, Sri Parameswaran
2011	J	`jnl`	Architectural Frameworks for Security and Reliability of MPSoCs. IEEE Trans. Very Large Scale Integr. Syst. Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
2011	A	`conf`	CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. ICCAD Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
2011	J	`jnl`	Configurable Multimode Embedded Floating-Point Units for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Yee Jern Chong, Sri Parameswaran
2011	A*	`conf`	Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study. DAC Haris Javaid, Muhammad Shafique, Sri Parameswaran, Jörg Henkel
2011	—	`conf`	Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos. ESTIMedia Hong Chinh Doan, Haris Javaid, Sri Parameswaran
2011	J	`jnl`	Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks. IET Comput. Digit. Tech. Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran, Aleksandar Ignjatovic
2011	Misc	`conf`	Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. VLSI Design Su Myat Min, Jorgen Peddersen, Sri Parameswaran
2011	A	`conf`	System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia. ICCAD Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran
2010	J	`jnl`	CASES 2009 guest editor's introduction. Des. Autom. Embed. Syst. Jörg Henkel, Sri Parameswaran
2010	A	`conf`	DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. DATE Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2010	A	`conf`	Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. DATE Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran
2010	A	`conf`	Fidelity metrics for estimation models. ICCAD Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2010	B	`conf`	Improved Architectures for Range Encoding in Packet Classification System. NCA Xin He, Jorgen Peddersen, Sri Parameswaran
2010	J	`jnl`	LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM. Des. Autom. Embed. Syst. Xin He, Jorgen Peddersen, Sri Parameswaran
2010	Misc	`conf`	Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications. CODES+ISSS Haris Javaid, Xin He, Aleksandar Ignjatovic, Sri Parameswaran
2010	—	`conf`	RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. DIPES/BICC Roshan G. Ragel, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran
2010	J	`jnl`	Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran
2010	A	`conf`	Rapid runtime estimation methods for pipelined MPSoCs. DATE Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran
2010	A*	`conf`	SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. DAC Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
2010	J	`jnl`	Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems. J. Syst. Archit. Hui Guo, Sri Parameswaran
2009	A*	`conf`	A design flow for application specific heterogeneous pipelined multiprocessor systems. DAC Haris Javaid, Sri Parameswaran
2009	A	`conf`	CUFFS: An instruction count based architectural framework for security of MPSoCs. DATE Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
2009	J	`jnl`	Custom Floating-Point Unit Generation for Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yee Jern Chong, Sri Parameswaran
2009	A	`conf`	Flexible multi-mode embedded floating-point unit for field programmable gate arrays. FPGA Yee Jern Chong, Sri Parameswaran
2009	J	`jnl`	HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. IET Comput. Digit. Tech. Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic
2009	—	`conf`	HitME: low power Hit MEmory buffer for embedded systems. ASP-DAC Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic
2009	Misc	`conf`	LOP: a novel SRAM-based architecture for low power and high throughput packet classification. CODES+ISSS Xin He, Jorgen Peddersen, Sri Parameswaran
2009	B	`conf`	LOP_RE: Range encoding for low power packet classification. LCN Xin He, Jorgen Peddersen, Sri Parameswaran
2009	Misc	`ed.`	Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009 CASES Jörg Henkel, Sri Parameswaran
2009	J	`jnl`	Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis. ACM Trans. Design Autom. Electr. Syst. Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran
2009	Misc	`conf`	Security and Dependability of Embedded Systems: A Computer Architects' Perspective. VLSI Design Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel
2009	Misc	`conf`	SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. CODES+ISSS Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran
2008	A	`conf`	A Formal Approach To The Protocol Converter Problem. DATE Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran
2008	Misc	`conf`	Anatomy of Differential Power Analysis for AES. SYNASC Jude Angelo Ambrose, Naeill Aldon, Aleksandar Ignjatovic, Sri Parameswaran
2008	J	`jnl`	Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG. Int. J. Parallel Program. Seng Lin Shee, Andrea Erdos, Sri Parameswaran
2008	J	`jnl`	Embedded systems security - an overview. Des. Autom. Embed. Syst. Sri Parameswaran, Tilman Wolf
2008	J	`jnl`	Energy Driven Application Self-Adaptation at Run-time. J. Comput. Jorgen Peddersen, Sri Parameswaran
2008	J	`jnl`	Guest editorial for special issue on embedded system security. Des. Autom. Embed. Syst. Tilman Wolf, Sri Parameswaran
2008	Misc	`conf`	LOCS: a low overhead profiler-driven design flow for security of MPSoCs. CODES+ISSS Krutartha Patel, Sri Parameswaran
2008	J	`jnl`	Low-Impact Processor for Dynamic Runtime Power Management. IEEE Des. Test Comput. Jorgen Peddersen, Sri Parameswaran
2008	A	`conf`	MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. ICCAD Jude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic
2008	—	`conf`	NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. ASP-DAC Jeremy Chan, Sri Parameswaran
2008	A*	`conf`	Rapid application specific floating-point unit generation with bit-alignment. DAC Yee Jern Chong, Sri Parameswaran
2008	A*	`conf`	SHIELD: a software hardware design methodology for security and reliability of MPSoCs. DAC Krutartha Patel, Sri Parameswaran
2008	Misc	`conf`	Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. CODES+ISSS Haris Javaid, Sri Parameswaran
2007	J	`jnl`	A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider. IEEE Trans. Circuits Syst. II Express Briefs Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
2007	Misc	`conf`	A smart random code injection to mask power analysis based side channel attacks. CODES+ISSS Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
2007	A	`conf`	Automatic application specific floating-point unit generation. DATE Yee Jern Chong, Sri Parameswaran
2007	—	`conf`	CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. ASP-DAC Jorgen Peddersen, Sri Parameswaran
2007	A*	`conf`	Design Methodology for Pipelined Heterogeneous Multiprocessor System. DAC Seng Lin Shee, Sri Parameswaran
2007	Misc	`conf`	Energy Driven Application SelfAdaptation. VLSI Design Jorgen Peddersen, Sri Parameswaran
2007	A	`conf`	Instruction trace compression for rapid instruction cache simulation. DATE Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel
2007	A*	`conf`	RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. DAC Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran
2006	—	`conf`	A novel instruction scratchpad memory optimization method based on concomitance metric. ASP-DAC Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
2006	Misc	`conf`	ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. VLSI Design Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
2006	Misc	`conf`	Application specific forwarding network and instruction encoding for multi-pipe ASIPs. CODES+ISSS Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic
2006	A	`conf`	Customization of application specific heterogeneous multi-pipeline processors. DATE Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
2006	J	`jnl`	Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. IEEE Trans. Very Large Scale Integr. Syst. Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
2006	—	`conf`	Finding optimal L1 cache configuration for embedded systems. ASP-DAC Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran
2006	Misc	`conf`	Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability. CODES+ISSS Roshan G. Ragel, Sri Parameswaran
2006	Misc	`conf`	Heterogeneous multiprocessor implementations for JPEG: : a case study. CODES+ISSS Seng Lin Shee, Andrea Erdos, Sri Parameswaran
2006	A*	`conf`	IMPRES: integrated monitoring for processor reliability and security. DAC Roshan G. Ragel, Sri Parameswaran
2005	—	`conf`	Balancing System Level Pipelines with Stage Voltage Scaling. ISVLSI Hui Guo, Sri Parameswaran
2005	—	`conf`	Battery-aware instruction generation for embedded processors. ASP-DAC Newton Cheung, Sri Parameswaran, Jörg Henkel
2005	J	`jnl`	Instruction code mapping for performance increase and energy reduction in embedded computer systems. IEEE Trans. Very Large Scale Integr. Syst. Sri Parameswaran, Jörg Henkel
2005	Misc	`conf`	Micro embedded monitoring for security in application specific instruction-set processors. CASES Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia
2005	A	`conf`	NoCEE: energy macro-model extraction methodology for network on chip routers. ICCAD Jeremy Chan, Sri Parameswaran
2005	Misc	`conf`	Novel architecture for loop acceleration: a case study. CODES+ISSS Seng Lin Shee, Sri Parameswaran, Newton Cheung
2005	Misc	`conf`	Rapid Embedded Hardware/Software System Generation. VLSI Design Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran
2005	B	`conf`	The effect of receiver front-end non-linearity on DS-UWB systems operating in the 3 to 4 GHz band. WCNC Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran
2004	A	`conf`	A quantitative study and estimation models for extensible instructions in embedded processors. ICCAD Newton Cheung, Sri Parameswaran, Jörg Henkel
2004	Misc	`conf`	Dual-pipeline heterogeneous ASIP design. CODES+ISSS Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran
2004	A	`conf`	Hardware/software managed scratchpad memory for embedded system. ICCAD Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic
2004	A	`conf`	MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. DATE Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan
2004	Misc	`conf`	NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. VLSI Design Jeremy Chan, Sri Parameswaran
2003	A	`conf`	INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. ICCAD Newton Cheung, Sri Parameswaran, Jörg Henkel
2003	—	`conf`	Multi-parametric improvements for embedded systems using code-placement and address bus coding. ASP-DAC Sri Parameswaran, Jörg Henkel, Haris Lekatsas
2003	—	`ch.`	Rapid Configuration & Instruction Selection for an ASIP: A Case Study. Embedded Software for SoC Newton Cheung, Jörg Henkel, Sri Parameswaran
2003	A	`conf`	Rapid Configuration and Instruction Selection for an ASIP: A Case Study. DATE Newton Cheung, Jörg Henkel, Sri Parameswaran
2003	Misc	`conf`	Specification and Design of Multi-Million Gate SOCs. VLSI Design Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran
2002	—	`ed.`	Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002 CODES Jörg Henkel, Xiaobo Sharon Hu, Rajesh Gupta, Sri Parameswaran
2002	—	`conf`	SWASAD: An ASIC Design for High Speed DNA Sequence Matching. ASP-DAC/VLSI Design Tony Han, Sri Parameswaran
2001	A	`conf`	Code placement in hardware/software co-synthesis to improve performance and reduce cost. DATE Sri Parameswaran
2001	A	`conf`	I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. ICCAD Sri Parameswaran, Jörg Henkel
2000	A*	`conf`	High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. DAC Vince E. Boros, Aleksandar D. Rakic, Sri Parameswaran
2000	J	`jnl`	Profiling in the ASP codesign environment. J. Syst. Archit. Sri Parameswaran, Matthew F. Parkinson, Peter L. Bartlett
2000	—	`conf`	Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. ASP-DAC Allan Rae, Sri Parameswaran
1998	—	`conf`	Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. ISSS Allan Rae, Sri Parameswaran
1998	—	`conf`	HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial). ASP-DAC Sri Parameswaran
1998	—	`conf`	Power Reduction in Pipelines. ASP-DAC Sri Parameswaran, Hui Guo
1998	—	`conf`	Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. ASP-DAC Hui Guo, Sri Parameswaran
1997	—	`conf`	Power consumption in CMOS combinational logic blocks at high frequencies. ASP-DAC Sri Parameswaran, Hui Guo
1995	—	`conf`	Profiling in the ASP codesign environment. ISSS Matthew F. Parkinson, Sri Parameswaran
1995	—	`conf`	Reclocking for high-level synthesis. ASP-DAC Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran
1994	—	`conf`	Design automation of self checking circuits. EURO-DAC Sayed Mohammad Kia, Sri Parameswaran
1994	Misc	`conf`	Novel architectures for TSC/CD and SFS/SCD synchronous controllers. VTS Sayed Mohammad Kia, Sri Parameswaran