Sreehari Veeramachaneni

54 papers C 2Misc 10Journal 17Unranked 25
YearRankTypeTitle / Venue / Authors
2025 J jnl
Addressing Adversarial Attacks in IoT Using Deep Learning AI Models.
IEEE Access
Sesibhushana Rao Bommana, Sreehari Veeramachaneni, Syed Ershad Ahmed, M. B. Srinivas
2025 J jnl
Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications.
CoRR
L. Hemanth Krishna, Srinivasu Bodapati, Sreehari Veeramachaneni, Bhaskara Rao Jammu, Noor Mahammad Sk
2025 J jnl
Energy-Efficient Decoding and Encoding Hardware for Optimized Posit Arithmetic.
IEEE Embed. Syst. Lett.
Aditya Anirudh Jonnalagadda, Rishi Thotli, Sreehari Veeramachaneni, Uppugunduru Anil Kumar, Syed Ershad Ahmed
2025 J jnl
Implementation of exact and approximate adder based divider for error resilient applications.
Discov. Comput.
Veerabadra Chary Rasoju, Anil Kumar Uppugunduru, Abhay Shriram, Sreehari Veeramachaneni, Syed Ershad Ahmed
2025 Misc conf
Optimizing Multipliers: An Energy-Efficient Design Using a Novel 3: 2 Compressor.
VLSID
L. Hemanth Krishna, Sreehari Veeramachaneni, Srinivasu Bodapati, Bhaskara Rao Jammu, Sk. Noor Mahammad
2024 J jnl
ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks.
IEEE Access
Aditya Anirudh Jonnalagadda, Uppugunduru Anil Kumar, Rishi Thotli, Satvik Sardesai, Sreehari Veeramachaneni, Syed Ershad Ahmed
2024 — conf
Bistable Physically Unclonable Function with Dynamic Threshold Voltage.
MWSCAS
Sesibhushana Rao Bommana, Sreehari Veeramachaneni, M. B. Srinivas
2024 J jnl
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor.
IEEE Embed. Syst. Lett.
L. Hemanth Krishna, Ayesha Sk, J. Bhaskara Rao, Sreehari Veeramachaneni, Sk. Noor Mahammad
2024 — conf
Energy-Efficient Ternary Multiplier.
AICAS
Rishi Agrawal, Narayanabhatla Savyasachi Abhijith, Uppugunduru Anil Kumar, Sreehari Veeramachaneni, Syed Ershad Ahmed
2024 Misc conf
Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems.
VLSID
Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad
2023 — conf
Design of Energy Efficient Posit Multiplier.
ACM Great Lakes Symposium on VLSI
Aditya Anirudh Jonnalagadda, Anil Kumar Uppugunduru, Sreehari Veeramachaneni, Syed Ershad Ahmed
2023 — conf
Highly Accurate Approximate Ternary Multipliers for Error Resilient Applications.
ISED
Shalini Burri, Gowtham Sri Harsha Kudulla, Pavan Kumar Jogi, Anantha Sai Satwik Vysyaraju, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni
2023 J jnl
Optimized Fault-Tolerant Adder Design Using Error Analysis.
J. Circuits Syst. Comput.
Raghavendra Kumar Sakali, P. Balasubramanian, Ramesh Reddy, Sreehari Veeramachaneni, Sk. Noor Mahammad
2023 — conf
Power Efficient Approximate Ternary Subtractor for Image Processing Applications.
iSES
Sangireddy Tharuni, Basani Harshavardhan Reddy, Bhukya Mamatha, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni
2023 J jnl
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs.
Integr.
Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad
2022 J jnl
A Low Error, Hardware Efficient Logarithmic Multiplier.
Circuits Syst. Signal Process.
L. Guna Sekhar Sai Harsha, Bhaskara Rao Jammu, Nalini Bodasingi, Sreehari Veeramachaneni, Noor Mohammad S.
2022 J jnl
A New Approximate 4-2 Compressor using Merged Sum and Carry.
J. Electron. Test.
Chinthalgiri Jyothi, Saranya Karunamurthi, Bhaskara Rao Jammu, Sreehari Veeramachaneni, Sk. Noor Mahammad
2022 J jnl
Hardware efficient circuit for low error logarithmic converter.
J. Comput. Methods Sci. Eng.
Bhaskara Rao Jammu, L. Guna Sekhar Sai Harsha, Nalini Bodasingi, Sreehari Veeramachaneni, Noor Mohammad S.
2022 — conf
Logic Locking Designs at Transistor Level for Full Adders.
iSES
Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad
2021 J jnl
A low-error, memory-based fast binary antilogarithmic converter.
Int. J. Circuit Theory Appl.
L. Guna Sekhar Sai Harsha, Bhaskara Rao Jammu, Visweswara Rao Samoju, Sreehari Veeramachaneni, Noor Mohammad S.
2021 — conf
Design and Analysis of Obfuscated Full Adders.
ICM
Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad
2021 J jnl
Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication.
IET Comput. Digit. Tech.
L. Hemanth Krishna, Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, S. K. Noor Mahammad
2021 — conf
Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications.
ICECS
L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, S. K. Noor Mahammad
2021 — conf
Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications.
iSES
L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad
2021 J jnl
Energy efficient signed and unsigned radix 16 booth multiplier design.
Comput. Electr. Eng.
Y. Mounica, K. Naresh Kumar, Sreehari Veeramachaneni, S. K. Noor Mahammad
2020 J jnl
Efficient implementation of mixed-precision multiply-accumulator unit for AI algorithms.
Int. J. Circuit Theory Appl.
Chandana Mounica, Sagar Krishna, Sreehari Veeramachaneni, Sk. Noor Mahammad
2018 Misc conf
An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications.
VLSID
Mahesh Kumar Adimulam, Amit Kapoor, Sreehari Veeramachaneni, M. B. Srinivas
2014 — conf
A New Design of an N-Bit Reversible Arithmetic Logic Unit.
ISED
Subhankar Pal, Chetan Kumar Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika
2014 Misc conf
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units.
VLSID
B. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni, M. B. Srinivas
2014 Misc conf
An Optimized Design of Reversible Quantum Comparator.
VLSID
P. Sai Phaneendra, Chetan Kumar Vudadha, Sreehari Veeramachaneni, M. B. Srinivas
2012 — conf
A Modified Twin Precision Multiplier with 2D Bypassing Technique.
ISED
Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2012 — conf
CNFET based ternary magnitude comparator.
ISCIT
Chetan Kumar Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas
2012 — conf
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.
ISVLSI
Chetan Kumar Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
2012 — conf
Design of Prefix-Based Optimal Reversible Comparator.
ISVLSI
Chetan Kumar Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
2012 Misc conf
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.
VLSI Design
Chetan Kumar Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter.
ISED
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
A Prefix Based Reconfigurable Adder.
ISVLSI
Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.
ISED
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 C conf
A Unified Architecture for BCD and Binary Adder/Subtractor.
DSD
Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2011 — conf
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
ISCIT
P. Sai Phaneendra, Chetan Kumar Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2010 — conf
A Novel, Variable Resolution Flash ADC with Sub Flash Architecture.
ISVLSI
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2010 — conf
A low power, variable resolution two-step flash ADC.
ACM Great Lakes Symposium on VLSI
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas
2010 J jnl
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
J. Low Power Electron.
Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas
2010 Misc conf
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
VLSI Design
Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
2010 — conf
Low power, variable resolution pipelined analog to Digital converter with sub flash architecture.
APCCAS
Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas
2009 — conf
A High Performance Unified BCD and Binary Adder/Subtractor.
ISVLSI
Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas
2009 J jnl
A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter.
J. Low Power Electron.
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
2009 — conf
A novel low power, variable resolution pipelined ADC.
SoCC
Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas
2009 Misc conf
Design of a Low Power, Variable-Resolution Flash ADC.
VLSI Design
Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas
2008 Misc conf
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.
VLSI Design
Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas
2007 Misc conf
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.
VLSI Design
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
2007 C conf
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.
ISCAS
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
2007 — conf
Novel architectures for efficient (m, n) parallel counters.
ACM Great Lakes Symposium on VLSI
Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas
2007 — conf
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.
ISVLSI
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas