Sree Ranjani Rajendran

16 papers A 1Misc 1Journal 8Unranked 6
YearRankTypeTitle / Venue / Authors
2026 J jnl
Digital Twins Beyond Monitoring: A Survey on Predictive Control, Cybersecurity, and Storage Integration in PV-Enabled Smart Grids.
IEEE Access
Deepthi Pilakkat, Karthi Balasubramanian, Sree Ranjani Rajendran
2025 J jnl
Complexity Measures in Biomedical Signal Analysis: A Clinically-Grounded Survey Across EEG, ECG, Intracranial Pressure, and Photoplethysmogram Modalities.
IEEE Access
Karthi Balasubramanian, Sree Ranjani Rajendran, Sandipan B. Pati
2025 J jnl
Deep Learning and Generative AI for Monolithic and Chiplet SoC Design and Verification: A Survey.
Found. Trends Electron. Des. Autom.
Imed Ben Dhaou, Syhem Larguech, Sree Ranjani Rajendran, Rajat Subhra Chakraborty, Hannu Tenhunen, Ahmed Abdelgawad
2025 J jnl
Scalable FPGA Implementation of a Reliability-Based Direct Turbo Decoder for Short Block Codes.
IEEE Access
Senthil Murugan, Ramesh Bhakthavatchalu, Karthi Balasubramanian, B. Yamuna, Deepak Mishra, Sree Ranjani Rajendran
2025 J jnl
Toward Intelligent Digital Twins for PV Systems: A Unified Framework for Control, Forecasting, and Grid Integration.
IEEE Access
Deepthi Pilakkat, Karthi Balasubramanian, Sree Ranjani Rajendran
2024 Misc conf
CAD Tools Pathway in Hardware Security.
VLSID
Sree Ranjani Rajendran, Farimah Farahmandi, Mark Tehranipoor
2024 J jnl
Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software.
IEEE Trans. Inf. Forensics Secur.
Sree Ranjani Rajendran, Nusrat Farzana Dipu, Shams Tarek, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor
2023 — conf
Benchmarking of SoC-Level Hardware Vulnerabilities: A Complete Walkthrough.
ISVLSI
Shams Tarek, Hasan Al Shaikh, Sree Ranjani Rajendran, Farimah Farahmandi
2023 A conf
HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities.
DATE
Sree Ranjani Rajendran, Shams Tarek, Benjamin M. Hicks, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor
2022 J jnl
A comprehensive survey of physical and logic testing techniques for Hardware Trojan detection and prevention.
J. Cryptogr. Eng.
Rijoy Mukherjee, Sree Ranjani Rajendran, Rajat Subhra Chakraborty
2022 — conf
Adiabatic Physical Unclonable Function Using Cross-Coupled Pair.
iSES
Vishnu Bajjuri, Nalesh S, Sree Ranjani Rajendran, S. Kala
2020 — conf
KARNA for a Trustable Hardware.
VDAT
Sree Ranjani Rajendran
2020 — conf
SoK: Physical and Logic Testing Techniques for Hardware Trojan Detection.
ASHES@CCS
Sree Ranjani Rajendran, Rijoy Mukherjee, Rajat Subhra Chakraborty
2018 — conf
A Novel Logical Locking Technique Against Key-Guessing Attacks.
ISED
Sree Ranjani Rajendran, M. Nirmala Devi
2018 — conf
Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks.
VDAT
Sree Ranjani Rajendran, M. Nirmala Devi
2017 J jnl
A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis.
IEEE Trans. Emerg. Top. Comput.
Rajat Subhra Chakraborty, Samuel Pagliarini, Jimson Mathew, Sree Ranjani Rajendran, M. Nirmala Devi