Spyros Tragoudas

268 papers A* 3A 19B 8C 39Misc 13Journal 94Unranked 88
YearRankTypeTitle / Venue / Authors
2026 J jnl
Improved Image Classification using Lightweight Deep Neural Network Enhancements.
ACM Trans. Intell. Syst. Technol.
Vasileios Pentsos, Spyros Tragoudas, Kiriti Nagesh Gowda, Mike Schmit
2025 J jnl
A Hybrid LSTM-Transformer Model for Power Load Forecasting.
IEEE Trans. Smart Grid
Vasileios Pentsos, Spyros Tragoudas, Jason Wibbenmeyer, Nasser Khdeer
2025 J jnl
A Statistical Method for Attack-Agnostic Adversarial Attack Detection with Compressive Sensing Comparison.
CoRR
Chinthana Wimalasuriya, Spyros Tragoudas
2025 — conf
A Vertical Approach to Designing and Managing Sustainable Heterogeneous Edge Data Centers.
ISVLSI
Aikaterini Maria Panteleaki, Varatheepan Paramanayakam, Vasileios Pentsos, Andreas Karatzas, Spyros Tragoudas, Iraklis Anagnostopoulos
2025 J jnl
A Vertical Approach to Designing and Managing Sustainable Heterogeneous Edge Data Centers.
CoRR
Aikaterini Maria Panteleaki, Varatheepan Paramanayakam, Vasileios Pentsos, Andreas Karatzas, Spyros Tragoudas, Iraklis Anagnostopoulos
2025 A conf
Deep Learning-based IC Monitoring.
ITC
Iresh M. Jayawardana, Krishna Dahal, Spyros Tragoudas, Khader S. Abdel-Hafez, Danushka Senarathna
2025 — conf
Energy-Aware DNN Task Scheduling with Dynamic Batching and Frequency Adjustment.
ISQED
Vasileios Pentsos, Spyros Tragoudas, Kiriti Nagesh Gowda, Mike Schmit
2025 J jnl
Time Series Analysis Neural Networks for Detecting False Data Injection Attacks of Different Rates on Power Grid State Estimation.
ACM Trans. Priv. Secur.
Danushka Senarathna, Spyros Tragoudas, Jason Wibbenmeyer, Nasser Khdeer
2024 C conf
Enhanced Distribution Matching for Multiclass Quantification.
ICMLA
Danuka Malinda, Danushka Senarathna, Spyros Tragoudas
2024 J jnl
Memristive Crossbar Array-Based Adversarial Defense Using Compression.
IEEE Trans. Emerg. Top. Comput.
Bijay Raj Paudel, Spyros Tragoudas
2023 C conf
A statistical approach to improve CNN classification accuracy.
HPSR
Vasileios Pentsos, Spyros Tragoudas
2023 C conf
Adversarial Defense using Memristors and Input Preprocessing
ISCAS
Bijay Raj Paudel, Spyros Tragoudas
2023 C conf
An Enhanced YOLO Failure Detection Method.
ICMLA
Danushka Senarathna, Rezoan Ferdous, Spyros Tragoudas
2023 — conf
Deep Neural Network-Based Accelerators for Repetitive Boolean Logic Evaluation.
SOCC
Danushka Senarathna, Spyros Tragoudas
2023 C conf
Detection and Quantization of Data Drift in Image Classification Neural Networks.
HPSR
Danushka Senarathna, Spyros Tragoudas, Kiriti Nagesh Gowda, Mike Schmit
2023 — conf
High Precision Winner-Take-All Circuit for Neural Networks.
SOCC
Bijay Raj Paudel, Haibo Wang, Spyros Tragoudas, Omkar Rijal
2022 C conf
Compressed Learning in MCA Architectures to Tolerate Malicious Noise.
IOLTS
Bijay Raj Paudel, Spyros Tragoudas
2022 — conf
Computation of Soft Error Rates Considering Test Pattern Sequences.
ISQED
Danushka Senarathna, Spyros Tragoudas
2022 J jnl
High-Speed Memristive Ternary Content Addressable Memory.
IEEE Trans. Emerg. Top. Comput.
Krishna Prasad Gnawali, Spyros Tragoudas
2022 J jnl
Improving the Forecasting and Classification of Extreme Events in Imbalanced Time Series Through Block Resampling in the Joint Predictor-Forecast Space.
IEEE Access
Xiaoqian Chen, Lalit Gupta, Spyros Tragoudas
2022 — conf
On the Resiliency of an Analog Memristive Architecture against Adversarial Attacks.
ISQED
Bijay Raj Paudel, Vasileios Pentsos, Spyros Tragoudas
2022 A conf
The Impact of On-chip Training to Adversarial Attacks in Memristive Crossbar Arrays.
ITC
Bijay Raj Paudel, Spyros Tragoudas
2021 — conf
A Fault Model to Detect Design Errors in Combinational Circuits.
DFT
Puneet Ramesh Savanur, Spyros Tragoudas
2021 C conf
Improved CNN classification accuracy with the addition of shallow cascading CNNs.
ICMLA
Vasileios Pentsos, Bijay Raj Paudel, Spyros Tragoudas, Kiriti Nagesh Gowda, Mike Schmit
2021 C conf
Predicting YOLO Misdetection by Learning Grid Cell Consensus.
ICMLA
Bijay Raj Paudel, Danushka Senarathna, Haibo Wang, Spyros Tragoudas, Yao Hu, Shengbing Jiang
2021 C conf
Resiliency of SNN on Black-Box Adversarial Attacks.
ICMLA
Bijay Raj Paudel, Aashish Itani, Spyros Tragoudas
2020 C conf
Broadside ATPG for Low Power Trojans Detection using Built-in Current Sensors.
IOLTS
Basim Shanyour, Spyros Tragoudas
2020 J jnl
Radiation Hardened Latch Designs for Double and Triple Node Upsets.
IEEE Trans. Emerg. Top. Comput.
Adam Watkins, Spyros Tragoudas
2020 J jnl
Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays.
IEEE Trans. Very Large Scale Integr. Syst.
Pavan Kumar Javvaji, Spyros Tragoudas
2019 J jnl
Low Power Artificial Neural Network Architecture.
CoRR
Krishna Prasad Gnawali, Seyed Nima Mozaffari, Spyros Tragoudas
2019 J jnl
On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations.
IEEE Trans. Very Large Scale Integr. Syst.
Pavan Kumar Javvaji, Spyros Tragoudas
2018 J jnl
A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions.
IEEE Trans. Circuits Syst. I Regul. Pap.
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2018 — conf
A Method to Model Statistical Path Delays for Accurate Defect Coverage.
DFT
Pavan Kumar Javvaji, Spyros Tragoudas
2018 — conf
An Aging Resilient Neural Network Architecture.
NANOARCH
Seyed Nima Mozaffari, Krishna Prasad Gnawali, Spyros Tragoudas
2018 A conf
Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors.
ITC
Basim Shanyour, Spyros Tragoudas
2018 C conf
Scalable Fault Coverage Estimation of Sequential Circuits without Fault Injection.
ISCAS
Pavan Kumar Javvaji, Spyros Tragoudas, Ganesh Kondapuram
2018 — conf
Test set identification for improved delay defect coverage in the presence of statistical delays.
ISQED
Pavan Kumar Javvaji, Basim Shanyour, Spyros Tragoudas
2018 — conf
Threshold Voltage Extraction Using Static NBTI Aging.
DFT
Puneet Ramesh Savanur, Spyros Tragoudas
2017 A conf
A new method to identify threshold logic functions.
DATE
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2017 — conf
Aging-aware critical paths for process related validation in the presence of NBTI.
ISQED
Phaninder Alladi, Spyros Tragoudas
2017 J jnl
Delay Analysis for Current Mode Threshold Logic Gate Designs.
IEEE Trans. Very Large Scale Integr. Syst.
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas
2017 J jnl
Design Techniques for Direct Digital Synthesis Circuits with Improved Frequency Accuracy Over Wide Frequency Ranges.
J. Circuits Syst. Comput.
Stefan Leitner, Haibo Wang, Spyros Tragoudas
2017 J jnl
Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ahish Mysore Somashekar, Spyros Tragoudas
2017 C conf
Diagnosis with transition faults on embedded segments.
IOLTS
Theodoros Toulas, Spyros Tragoudas
2017 — conf
Efficient Critical Path Selection Under a Probabilistic Delay Model.
ACM Great Lakes Symposium on VLSI
Ahish Mysore Somashekar, Spyros Tragoudas
2017 C conf
Efficient computation of the sensitization probability of a critical path considering process variations and path correlation.
ISCAS
Pavan Kumar Javvaji, Spyros Tragoudas
2017 C conf
METS: A multiple event transient simulator.
ISCAS
Adam Watkins, Spyros Tragoudas
2017 J jnl
More Efficient Testing of Metal-Oxide Memristor-Based Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2017 C conf
Reducing power, area, and delay of threshold logic gates considering non-integer weights.
ISCAS
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2016 — conf
A Highly Robust Double Node Upset Tolerant latch.
DFT
Adam Watkins, Spyros Tragoudas
2016 J jnl
ATPG for Delay Defects in Current Mode Threshold Logic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis
2016 — conf
An Enhanced Analytical Electrical Masking Model for Multiple Event Transients.
ACM Great Lakes Symposium on VLSI
Adam Watkins, Spyros Tragoudas
2016 — conf
Compressive image sensor technique with sparse measurement matrix.
SoCC
Stefan Leitner, Haibo Wang, Spyros Tragoudas
2016 — conf
Efficient selection of critical paths for delay defects in the presence of process variations.
DTIS
Phaninder Alladi, Spyros Tragoudas
2016 — conf
Identification of delay defects on embedded paths using one current sensor.
DTIS
Wisam Aljubouri, Spyros Tragoudas, Themistoklis Haniotakis
2016 J jnl
Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection.
ACM Trans. Design Autom. Electr. Syst.
Ahish Mysore Somashekar, Spyros Tragoudas, Rathish Jayabharathi, Sreenivas Gangadhar
2015 — conf
A BIST approach for counterfeit circuit detection based on NBTI degradation.
DFTS
Puneet Ramesh Savanur, Phaninder Alladi, Spyros Tragoudas
2015 — conf
Fast march tests for defects in resistive memory.
NANOARCH
Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis
2015 C conf
Non-enumerative correlation-aware path selection.
ICCD
Ahish Mysore Somashekar, Spyros Tragoudas, Rathish Jayabharathi
2015 C conf
Towards Trojan circuit detection with maximum state transition exploration.
IOLTS
Joseph Lenox, Spyros Tragoudas
2015 — conf
Unreachable code identification for improved line coverage.
ISQED
Luke Pierce, Spyros Tragoudas
2014 — conf
A novel parallel adaptation of an implicit path delay grading method.
ACM Great Lakes Symposium on VLSI
Joseph Lenox, Spyros Tragoudas
2014 — conf
ATPG for transition faults of pipelined threshold logic circuits.
DTIS
Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis
2014 J jnl
Adapting an Implicit Path Delay Grading Method for Parallel Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Joseph Lenox, Spyros Tragoudas
2014 — conf
Adaptive compressive sensing for low power wireless sensors.
ACM Great Lakes Symposium on VLSI
Adam Watkins, Venkata Naresh Mudhireddy, Haibo Wang, Spyros Tragoudas
2014 C conf
Aging-aware critical paths in deep submicron.
IOLTS
Phaninder Alladi, Spyros Tragoudas
2014 — conf
Diagnosis of segment delay defects with current sensing.
DFT
Wisam Aljubouri, Ahish Mysore Somashekar, Themistoklis Haniotakis, Spyros Tragoudas
2014 J jnl
Error Correction Encoding for Tightly Coupled On-Chip Buses.
IEEE Trans. Very Large Scale Integr. Syst.
Kedar Karmarkar, Spyros Tragoudas
2014 J jnl
Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms.
ACM J. Emerg. Technol. Comput. Syst.
Ashok Kumar Palaniswamy, Spyros Tragoudas
2014 J jnl
Nanopipelined threshold network synthesis.
ACM J. Emerg. Technol. Comput. Syst.
Luke Pierce, Spyros Tragoudas
2014 J jnl
On-Chip Codeword Generation to Cope With Crosstalk.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kedar Karmarkar, Spyros Tragoudas
2014 J jnl
Scalable Offline Searches in DNA Sequences.
ACM J. Emerg. Technol. Comput. Syst.
Pragyan (Sheela) Mohanty, Spyros Tragoudas
2013 J jnl
A Probabilistic Approach to Diagnose SETs in Sequential Circuits.
J. Electron. Test.
Sreenivas Gangadhar, Spyros Tragoudas
2013 — conf
A method to determine the sensitization probability of a non-robustly testable path.
ISQED
Dheepakkumaran Jayaraman, Spyros Tragoudas
2013 — conf
Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements.
ISQED
Ahish Mysore Somashekar, Spyros Tragoudas
2013 J jnl
Enhanced Secure Architecture for Joint Action Test Group Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Luke Pierce, Spyros Tragoudas
2013 C conf
Error detection encoding for multi-threshold capture mechanism.
IOLTS
Kedar Karmarkar, Spyros Tragoudas
2013 — conf
Low power and high speed current-mode memristor-based TLGs.
DFTS
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas
2013 — conf
Performance validation through implicit removal of infeasible paths of the behavioral description.
ISQED
Dheepakkumaran Jayaraman, Spyros Tragoudas
2012 — conf
A scalable threshold logic synthesis method using ZBDDs.
ACM Great Lakes Symposium on VLSI
Ashok Kumar Palaniswamy, Spyros Tragoudas
2012 — conf
Accurate calculation of SET propagation probability for hardening.
DFT
Sreenivas Gangadhar, Spyros Tragoudas
2012 J jnl
An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic.
IEEE Trans. Computers
Michael N. Skoufis, Spyros Tragoudas
2012 J jnl
An efficient heuristic to identify threshold logic functions.
ACM J. Emerg. Technol. Comput. Syst.
Ashok Kumar Palaniswamy, Spyros Tragoudas
2012 — conf
Delay Analysis for an N-Input Current Mode Threshold Logic Gate.
ISVLSI
Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas
2012 C conf
Non-enumerative generation of statistical path delays for ATPG.
ICCD
Ahish Mysore Somashekar, Spyros Tragoudas, Sreenivas Gangadhar, Rathish Jayabharathi
2012 J jnl
Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission.
Ad Hoc Networks
Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas
2012 — conf
Transient pulse propagation using the Weibull distribution function.
DFT
Adam Watkins, Spyros Tragoudas
2011 — conf
A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate.
DFT
Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis
2011 — conf
A Probabilistic Approach to Diagnose SETs.
DFT
Sreenivas Gangadhar, Spyros Tragoudas
2011 — conf
A Scalable Method for Identifying DNA Substrings Using Functions.
BICoB
Pragyan P. Mohanty, Spyros Tragoudas
2011 Misc conf
An analytical method for estimating SET propagation.
VTS
Sreenivas Gangadhar, Spyros Tragoudas
2011 C conf
Error correction encoding for multi-threshold capture mechanism.
IOLTS
Kedar Karmarkar, Spyros Tragoudas
2011 J jnl
Improved diagnosis using enhanced fault dominance.
Integr.
Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
2011 C conf
Multi-level secure JTAG architecture.
IOLTS
Luke Pierce, Spyros Tragoudas
2011 — conf
Occurrence probability analysis of a path at the architectural level.
ISQED
Dheepakkumaran Jayaraman, Spyros Tragoudas
2010 J jnl
A Data Capturing Method for Buses on Chip.
IEEE Trans. Circuits Syst. I Regul. Pap.
Michael N. Skoufis, Kedar Karmarkar, Spyros Tragoudas, Themistoklis Haniotakis
2010 — conf
A novel probabilistic SET propagation method.
ISQED
Sreenivas Gangadhar, Spyros Tragoudas
2010 — conf
Gating internal nodes to reduce power during scan shift.
ACM Great Lakes Symposium on VLSI
Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas
2010 J jnl
Identification of Delay Measurable PDFs Using Linear Dependency Relationships.
IEEE Trans. Very Large Scale Integr. Syst.
Edward Flanigan, Spyros Tragoudas
2010 C conf
On-line detection of random voltage perturbations in buses with multiple-threshold receivers.
IOLTS
Michael N. Skoufis, Spyros Tragoudas
2010 C conf
Probabilistic methods for the impact of an SET in combinational logic.
IOLTS
Sreenivas Gangadhar, Spyros Tragoudas
2010 A conf
Scalable codeword generation for coupled buses.
DATE
Kedar Karmarkar, Spyros Tragoudas
2010 — conf
Scalable identification of threshold logic functions.
ACM Great Lakes Symposium on VLSI
Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, Spyros Tragoudas
2010 J jnl
Scan Shift Power Reduction by Gating Internal Nodes.
J. Low Power Electron.
Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas
2010 J jnl
Techniques to Prioritize Paths for Diagnosis.
IEEE Trans. Very Large Scale Integr. Syst.
Rajsekhar Adapa, Spyros Tragoudas
2009 — ed.
24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009
DFT
Dimitris Gizopoulos, Susumu Horiguchi, Spyros Tragoudas, Mohammad Tehranipoor
2009 Misc conf
Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions.
VTS
Edward Flanigan, Spyros Tragoudas, Arkan Abdulrahman
2008 — conf
A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks.
DFT
Manoj Kumar Goparaju, Ashok Kumar Palaniswamy, Spyros Tragoudas
2008 — conf
A High-Performance Bus Architecture for Strongly Coupled Interconnects.
ISQED
Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas
2008 Misc conf
A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates.
VTS
Manoj Kumar Goparaju, Spyros Tragoudas
2008 — conf
A Novel Test Generation Methodology for Adaptive Diagnosis.
ISQED
Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas
2008 — ch.
Graph Theory and Algorithms.
Wiley Encyclopedia of Computer Science and Engineering
Dimitri Kagaris, Spyros Tragoudas
2008 J jnl
Identification of Critical Executable Paths at the Architectural Level.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chunrong Song, Spyros Tragoudas
2008 A conf
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model.
ITC
Dheepakkumaran Jayaraman, Edward Flanigan, Spyros Tragoudas
2008 J jnl
Low-power multi-core ATPG to target concurrency.
Integr.
Arkan Abdulrahman, Spyros Tragoudas
2008 J jnl
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.
J. Electron. Test.
Kyriakos Christou, Maria K. Michael, Spyros Tragoudas
2008 — conf
Prioritization of Paths for Diagnosis.
DFT
Rajsekhar Adapa, Spyros Tragoudas
2008 C conf
Propagation of Transients Along Sensitizable Paths.
IOLTS
Sreenivas Gangadhar, Michael N. Skoufis, Spyros Tragoudas
2008 — conf
Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures.
ISQED
Edward Flanigan, Arkan Abdulrahman, Spyros Tragoudas
2007 — conf
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations.
ISQED
Manoj Kumar Goparaju, Spyros Tragoudas
2007 Misc conf
Accelerating Diagnosis via Dominance Relations between Sets of Faults.
VTS
Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
2007 — conf
Enhanced Identification of Strong Robustly Testable Paths.
ISQED
Edward Flanigan, Spyros Tragoudas
2007 — conf
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture.
ISQED
Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov
2007 Misc conf
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.
VLSI Design
Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov
2007 — conf
Glitch Control with Dynamic Receiver Threshold Adjustment.
ISQED
Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas
2007 J jnl
High-Quality Transition Fault ATPG for Small Delay Defects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas
2007 J jnl
Managing the power resources of sensor networks with performance considerations.
Comput. Commun.
Khadija Jirari Stewart, Spyros Tragoudas
2007 J jnl
Speedups in embedded systems with a high-performance coprocessor datapath.
ACM Trans. Design Autom. Electr. Syst.
Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis
2006 — conf
A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates.
DFT
Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas
2006 J jnl
A high-performance data path for synthesizing DSP kernels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
2006 — conf
An Improved Method for Identifying Linear Dependencies in Path Delay Faults.
ISQED
Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas
2006 C conf
Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding.
IOLTS
Stelios Neophytou, Maria K. Michael, Spyros Tragoudas
2006 — conf
Evaluation of Collapsing Methods for Fault Diagnosis.
ISQED
Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
2006 A conf
Exact At-speed Delay Fault Grading in Sequential Circuits.
ITC
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi
2006 J jnl
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi
2006 J jnl
Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Stelios Neophytou, Maria K. Michael, Spyros Tragoudas
2006 — conf
Implicit Critical PDF Test Generation with Maximal Test Efficiency.
DFT
Kyriakos Christou, Maria K. Michael, Spyros Tragoudas
2006 J jnl
Implicit grading of multiple path delay faults.
ACM Trans. Design Autom. Electr. Syst.
Saravanan Padmanaban, Spyros Tragoudas
2006 J jnl
InTeRail: A Test Architecture for Core-Based SOCs.
IEEE Trans. Computers
Dimitri Kagaris, Spyros Tragoudas, Sherin Kuriakose
2006 Misc conf
Interconnect Testing for Networks on Chips.
VTS
Khadija Jirari Stewart, Spyros Tragoudas
2006 — conf
Minimizing FPGA Reconfiguration Data at Logic Level.
ISQED
Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas
2006 — conf
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level.
ISQED
Arkan Abdulrahman, Spyros Tragoudas
2006 C conf
Sub-faults identification for collapsing in diagnosis.
ISCAS
Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael
2005 — conf
A Minimum Cut Based Re-Synthesis Approach.
ISQED
M. Welling, Spyros Tragoudas, Haibo Wang
2005 Misc conf
A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs.
VLSI Design
Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas
2005 J jnl
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels.
J. Circuits Syst. Comput.
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
2005 B conf
A security protocol for sensor networks.
GLOBECOM
Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas
2005 — conf
Design and Evaluation of a Security Scheme for Sensor Networks.
ISQED
Khadija Jirari Stewart, Themistoklis Haniotakis, Spyros Tragoudas
2005 J jnl
Efficient identification of (critical) testable path delay faults using decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saravanan Padmanaban, Spyros Tragoudas
2005 J jnl
Function-based compact test pattern generation for path delay faults.
IEEE Trans. Very Large Scale Integr. Syst.
Maria K. Michael, Spyros Tragoudas
2005 — conf
Functions for Quality Transition Fault Tests.
ISQED
Maria K. Michael, Stelios Neophytou, Spyros Tragoudas
2005 A conf
Implicit and Exact Path Delay Fault Grading in Sequential Circuits.
DATE
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi
2005 J jnl
Low Power Test Generation for Path Delay Faults.
J. Low Power Electron.
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas
2005 — conf
Low power test generation for path delay faults using stability functions.
ACM Great Lakes Symposium on VLSI
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas
2005 J jnl
On-chip embedding mechanisms for large sets of vectors for delay test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Spyros Tragoudas, Vijay Nagarandal
2005 C conf
Quality Transition Fault Tests Suitable for Small Delay Defects.
ICCD
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas
2005 — conf
Reduced Test Application Time Based on Reachability Analysis.
ISQED
Themistoklis Haniotakis, Spyros Tragoudas, G. Pani
2005 J jnl
Rewiring for watermarking digital circuit netlists.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
M. Moiz Khan, Spyros Tragoudas
2005 — conf
Test set enhancement for quality transition faults using function-based methods.
ACM Great Lakes Symposium on VLSI
Stelios Neophytou, Maria K. Michael, Spyros Tragoudas
2005 C conf
Towards finding path delay fault tests with high test efficiency using ZBDDs.
ICCD
Maria K. Michael, Kyriakos Christou, Spyros Tragoudas
2004 A conf
A Critical Path Selection Method for Delay Testing.
ITC
Saravanan Padmanaban, Spyros Tragoudas
2004 — conf
A Novel Data-Path for Accelerating DSP Kernels.
SAMOS
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
2004 — conf
A high performance data-path to accelerate DSP kernels.
ICECS
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis
2004 A conf
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels.
FPGA
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
2004 J jnl
A unified framework for generating all propagation functions for logic errors and events.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas
2004 Misc conf
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path.
FCCM
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
2004 — conf
An Adaptive Path Delay Fault Diagnosis Methodology.
ISQED
Saravanan Padmanaban, Spyros Tragoudas
2004 — conf
Compact ATPG for Concurrent SOC Testing.
MTV
Arkan Abdulrahman, Spyros Tragoudas
2004 — conf
Identification of Gates for Covering all Critical Paths.
MTV
M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu
2004 J jnl
Implicit deductive fault simulation for complex delay fault models.
IEEE Trans. Very Large Scale Integr. Syst.
J. V. Deodhar, Spyros Tragoudas
2004 — conf
Low power ATPG for path delay faults.
ACM Great Lakes Symposium on VLSI
Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas
2004 — conf
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.
PATMOS
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
2004 B conf
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path.
FPL
Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis
2004 A conf
On-line Testing Field Programmable Analog Array Circuits.
ITC
Haibo Wang, Suchitra Kulkarni, Spyros Tragoudas
2004 — conf
Rewiring for Watermarking Digital Circuits.
ISQED
M. Moiz Khan, Spyros Tragoudas
2004 — conf
Security enhancement through multiple path transmission in ad hoc networks.
ICC
Themistoklis Haniotakis, Spyros Tragoudas, Constantinos Kalapodas
2004 A conf
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults.
DATE
Saravanan Padmanaban, Spyros Tragoudas
2003 J jnl
An implicit path-delay fault diagnosis methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saravanan Padmanaban, Spyros Tragoudas
2003 J jnl
Exact path delay fault coverage with fundamental ZBDD operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas
2003 — conf
Generation of Hazard Identification Functions.
ISQED
Maria K. Michael, Spyros Tragoudas
2003 C conf
InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs.
IOLTS
Dimitri Kagaris, Spyros Tragoudas
2003 J jnl
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds.
J. Electron. Test.
Dimitri Kagaris, Spyros Tragoudas
2003 A conf
Non-Enumerative Path Delay Fault Diagnosis .
DATE
Saravanan Padmanaban, Spyros Tragoudas
2003 J jnl
Path delay fault testing using test points.
ACM Trans. Design Autom. Electr. Syst.
Spyros Tragoudas, N. Denny
2002 J jnl
A new built-in TPG method for circuits with random patternresistant faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas
2002 J jnl
ATPG tools for delay faults at the functional level.
ACM Trans. Design Autom. Electr. Syst.
Maria K. Michael, Spyros Tragoudas
2002 J jnl
An efficient algorithm for finding a path subject to two additive constraints.
Comput. Commun.
Turgay Korkmaz, Marwan Krunz, Spyros Tragoudas
2002 J jnl
Disjoint Paths with Length Constraints.
Int. J. Comput. Their Appl.
Spyros Tragoudas, Yaakov L. Varol
2002 A conf
Exact Grading of Multiple Path Delay Faults.
DATE
Saravanan Padmanaban, Spyros Tragoudas
2002 J jnl
On the nonenumerative path delay fault simulation problem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dimitrios Kagaris, Spyros Tragoudas
2002 J jnl
Using a WLFSR to Embed Test Pattern Pairs in Minimum Time.
J. Electron. Test.
Dimitrios Kagaris, Spyros Tragoudas
2001 — conf
ATPG for Path Delay Faults without Path Enumeration.
ISQED
Maria K. Michael, Spyros Tragoudas
2001 — conf
Color Counting and its Application to Path Delay Fault Coverage.
ISQED
Jayant Deodhar, Spyros Tragoudas
2001 J jnl
Computational analysis of counter-based schemes for VLSI test pattern generation.
Discret. Appl. Math.
Dimitrios Kagaris, Spyros Tragoudas
2001 A conf
Exact path delay grading with fundamental BDD operations.
ITC
Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas
2001 J jnl
The most reliable data-path transmission.
IEEE Trans. Reliab.
Spyros Tragoudas
2001 — conf
Using a WLFSR to Embed Test Pattern Pairs in Minimum Time.
IOLTW
Dimitri Kagaris, Spyros Tragoudas
2001 J jnl
Von Neumann hybrid cellular automata for generating deterministic test sequences.
ACM Trans. Design Autom. Electr. Syst.
Dimitrios Kagaris, Spyros Tragoudas
2000 A* conf
An efficient algorithm for finding a path subject to two additive constraints.
SIGMETRICS
Turgay Korkmaz, Marwan Krunz, Spyros Tragoudas
2000 C conf
Methods for on-chip embedding of path delay test vectors.
ISCAS
Dimitri Kagaris, Spyros Tragoudas
2000 B conf
Power dissipation component of a management protocol for ad-hoc networks.
WCNC
Spyros Tragoudas
2000 C conf
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds.
ICCD
Dimitrios Kagaris, Spyros Tragoudas
2000 B conf
Routing with energy considerations in mobile ad-hoc networks.
WCNC
Spyros Tragoudas, S. Dimitrova
2000 J jnl
Test-set partitioning for multi-weighted random LFSRs.
Integr.
Dimitri Kagaris, Spyros Tragoudas, Amitava Majumdar
1999 J jnl
A fast nonenumerative automatic test pattern generator for pathdelay faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Spyros Tragoudas, Dimitrios Karayiannis
1999 A conf
ATPG Tools for Delay Faults at the Functional Level.
DATE
Spyros Tragoudas, Maria K. Michael
1999 A conf
Accurate path delay fault coverage is feasible.
ITC
Spyros Tragoudas
1999 J jnl
Board-level partitioning for partial scan using fuzzy logic.
IEEE Trans. Fuzzy Syst.
Spyros Tragoudas, Ralf Münzenberger, Kenneth J. Danhof
1999 — ch.
CAD Tools for BIST/DFT and Delay Faults.
The VLSI Handbook
Spyros Tragoudas
1999 Misc conf
Disjoint paths with length constraints.
CATA
Spyros Tragoudas, Yaakov L. Varol
1999 — conf
Embedded cores using built-in mechanisms.
ISCAS (1)
Dimitrios Kagaris, Spyros Tragoudas
1999 — conf
Functional ATPG for Delay Faults.
Great Lakes Symposium on VLSI
Spyros Tragoudas, Maria K. Michael
1999 — conf
LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles.
DFT
Dimitrios Kagaris, Spyros Tragoudas
1999 J jnl
Maximum weighted independent sets on transitive graphs and applications1.
Integr.
Dimitri Kagaris, Spyros Tragoudas
1999 J jnl
On the design of optimal counter-based schemes for test set embedding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dimitrios Kagaris, Spyros Tragoudas
1999 — conf
Testing for Path Delay Faults Using Test Points.
DFT
Spyros Tragoudas, N. Denny
1999 C conf
The most reliable data path transmission.
IPCCC
Spyros Tragoudas
1999 J jnl
Transmissions in a network with capacities and delays.
Networks
Dimitrios Kagaris, Grammati E. Pantziou, Spyros Tragoudas, Christos D. Zaroliagis
1998 Misc conf
A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults.
VTS
Dimitrios Karayiannis, Spyros Tragoudas
1998 J jnl
Clustering Network Modules with Different Implementations for Delay Minimization.
VLSI Design
Dimitrios Karayiannis, Spyros Tragoudas
1998 — conf
On-Chip Test Embedding for Multi-Weighted Random LFSRs.
DFT
Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar
1998 J jnl
Timing-Driven Circuit Implementation.
VLSI Design
Dimitrios Karayiannis, Spyros Tragoudas
1997 — conf
Cellular automata for generating deterministic test sequences.
ED&TC
Dimitrios Kagaris, Spyros Tragoudas
1997 J jnl
Implementing and clustering modules with complex delays.
Integr.
Spyros Tragoudas, Dimitrios Karayiannis
1997 J jnl
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis
1997 A conf
Maximum independent sets on transitive graphs and their applications in testing and CAD.
ICCAD
Dimitrios Kagaris, Spyros Tragoudas
1997 C conf
Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms.
ICCD
Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis
1996 J jnl
A fast algorithm for minimizing FPGA combinational and sequential modules.
ACM Trans. Design Autom. Electr. Syst.
Dimitrios Kagaris, Spyros Tragoudas
1996 C conf
A multiseed counter TPG with performance guarantee.
ICCD
Dimitrios Kagaris, Spyros Tragoudas
1996 A conf
ATPD: An Automatic Test Pattern Generator for Path Delay Faults.
ITC
Dimitrios Karayiannis, Spyros Tragoudas
1996 B conf
Computing Disjoint Path with Lenght Constraints.
WG
Spyros Tragoudas, Yaakov L. Varol
1996 — conf
Deterministic Test Pattern Reproduction by a Counter.
ED&TC
Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar
1996 C conf
FPGA Module Minimization.
ICCD
D. Kuguris, Spyros Tragoudas
1996 Misc conf
Generating deterministic unordered test patterns with counters.
VTS
Dimitrios Kagaris, Spyros Tragoudas
1996 J jnl
Improved Approximations for the Minimum-Cut Ratio and the Flux.
Math. Syst. Theory
Spyros Tragoudas
1996 J jnl
Min-Cut Partitioning on Underlying Tree and Graph Structures.
IEEE Trans. Computers
Spyros Tragoudas
1996 J jnl
On the Use of Counters for Reproducing Deterministic Test Sets.
IEEE Trans. Computers
Dimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar
1996 J jnl
Retiming-Based Partial Scan.
IEEE Trans. Computers
Dimitrios Kagaris, Spyros Tragoudas
1995 J jnl
Avoiding linear dependencies in LFSR test pattern generators.
J. Electron. Test.
Dimitrios Kagaris, Spyros Tragoudas
1995 J jnl
Bipartitioning into Overlapping Sets.
Int. J. Found. Comput. Sci.
James Haralambides, Spyros Tragoudas
1995 J jnl
Fast Approximation Algorithms for Multicommodity Flow Problems.
J. Comput. Syst. Sci.
Frank Thomson Leighton, Fillia Makedon, Serge A. Plotkin, Clifford Stein, Éva Tardos, Spyros Tragoudas
1995 B conf
On the Computation of Fast Data Transmissions in Networks with Capacities and Delays.
WADS
Dimitrios Kagaris, Spyros Tragoudas, Grammati E. Pantziou, Christos D. Zaroliagis
1995 J jnl
Pseudo-exhaustive built-in TPG for sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
1995 — conf
Quickest paths: parallelization and dynamization .
HICSS (2)
Dimitrios Kagaris, Spyros Tragoudas, Grammati E. Pantziou, Christos D. Zaroliagis
1995 — conf
Uniform area timing-driven circuit implementation.
Great Lakes Symposium on VLSI
Dimitrios Karayiannis, Spyros Tragoudas
1994 C conf
A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators.
ICCD
Dimitrios Kagaris, Spyros Tragoudas
1994 Misc conf
A design for testability technique for test pattern generation with LFSRs.
VTS
Dimitrios Kagaris, Spyros Tragoudas
1994 J jnl
A method for pseudo-exhaustive test pattern generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas
1994 — conf
An improved algorithm for the generalized min-cut partitioning problem.
Great Lakes Symposium on VLSI
Spyros Tragoudas
1994 Misc conf
High Performance Over-the-Cell Routing.
VLSI Design
Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani
1994 — conf
Mathematical model for routability analysis of FPGAs.
Great Lakes Symposium on VLSI
Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas
1994 J jnl
On Channel Routing Problems With Interchangeable Terminals.
VLSI Design
Spyros Tragoudas
1994 — conf
Retiming algorithms with application to VLSI testability.
Great Lakes Symposium on VLSI
Dimitrios Kagaris, Spyros Tragoudas
1994 J jnl
The Problem of Partitioning with Duplications and its Applications.
Int. J. Artif. Intell. Tools
James Haralambides, Spyros Tragoudas
1993 — ch.
Approximate solutions for Graph and Hypergraph Partitioning.
Algorithmic Aspects of VLSI Layout
Fillia Makedon, Spyros Tragoudas
1993 J jnl
Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets.
IEEE Trans. Very Large Scale Integr. Syst.
Dimitrios Kagaris, Spyros Tragoudas
1993 — conf
Minmax-cut graph partitioning problems.
Great Lakes Symposium on VLSI
Spyros Tragoudas
1993 A* conf
Partial Scan with Retiming.
DAC
Dimitrios Kagaris, Spyros Tragoudas
1993 C conf
Pseudoexhaustive BIST for Sequential Circuits.
ICCD
Dimitrios Kagaris, Spyros Tragoudas, Dinesh Bhatia
1993 J jnl
River routing and density minimization for channels with interchangeable terminals.
Integr.
Spyros Tragoudas, Ioannis G. Tollis
1993 J jnl
Searching a Pseudo 3-Sided Solid Orthoconvex Grid.
Int. J. Found. Comput. Sci.
Antonios Symvonis, Spyros Tragoudas
1992 J jnl
Circuit partitioning into small sets.
Microprocess. Microsystems
Spyros Tragoudas, Fillia Makedon, Robert Farell
1992 C conf
On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability.
ICCD
Dimitrios Kagaris, Fillia Makedon, Spyros Tragoudas
1992 B conf
Searching a Solid Pseudo 3-Sided Orthoconvex Grid.
ISAAC
Antonios Symvonis, Spyros Tragoudas
1991 J jnl
A comparative study of five language independent programming environments.
J. Syst. Softw.
Panayiotis E. Pintelas, Spyros Tragoudas
1991 — conf
Circuit partitioning into small sets: a tool to support testing with further applications.
EURO-DAC
Spyros Tragoudas, R. Farrell, Fillia Makedon
1991 A* conf
Fast Approximation Algorithms for Multicommodity Flow Problems
STOC
Frank Thomson Leighton, Fillia Makedon, Serge A. Plotkin, Clifford Stein, Éva Tardos, Spyros Tragoudas
1990 B conf
Approximating the minimum net expansion: Near optimal solutions to circuit partitioning problems.
WG
Fillia Makedon, Spyros Tragoudas