Sourajeet Roy

14 papers A* 1A 1Misc 1Journal 9Unranked 2
YearRankTypeTitle / Venue / Authors
2025 A conf
Continuous On-Chip Learning in Neural Networks using SOT-MRAM based CIM Architectures.
ICCAD
Anubha Sehgal, Sandeep Soni, Sumit Diware, Alok Kumar Shukla, Sourajeet Roy, Rajendra Bishnoi
2025 A* conf
Enhancing Parallelism and Energy-Efficiency in SOT-MRAM based CIM Architecture for On-Chip Learning.
DAC
Anubha Sehgal, Alok Kumar Shukla, Sumit Diware, Sandeep Soni, Seema Dhull, Sonal Shreya, Sourajeet Roy, Rajendra Bishnoi
2025 J jnl
Metalearning Based Adaptive Compact Modeling Framework for Advanced Transistors Across Technology Nodes.
IEEE Trans. Artif. Intell.
Srishti Parandiyal, Abhishek Kumar, M. Ehteshamuddin, Anamika Singh, Kumar Sheelvardhan, Samrat Ray, Abhishek Somani, Sourajeet Roy, Avirup Dasgupta
2025 J jnl
Scientific machine learning for generic compact model parameter extraction of nanoscale transistors.
Eng. Appl. Artif. Intell.
Kumar Sheelvardhan, Surila Guglani, Abhilash Dubey, Shashank Dubey, Sindhu Ramaswamy, Vaidy Subramanian, Kassandra Anderson, Glenn Workman, Sourajeet Roy, Avirup Dasgupta
2023 J jnl
Fast Multi-ANN Composite Models for Repeater Optimization in Presence of Parametric Uncertainty for on-Chip Hybrid Copper-Graphene Interconnects.
IEEE Access
Suyash Kushwaha, Avirup Dasgupta, Sourajeet Roy, Rohit Sharma
2022 J jnl
A Bilevel Multi-Fidelity Polynomial Chaos Approach for the Uncertainty Quantification of MWCNT Interconnect Networks With Variable Imperfect Contact Resistances.
IEEE Access
Surila Guglani, K. M. Dimple, Sourajeet Roy, Rohit Sharma, Brajesh Kumar Kaushik
2022 — conf
Artificial Neural Network Surrogate Models for Efficient Design Space Exploration of 14-nm FinFETs.
DRC
Surila Guglani, Avirup Dasgupta, Ming-Yen Kao, Chenming Hu, Sourajeet Roy
2022 Misc conf
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications.
VLSID
Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta
2020 — conf
Statistical Analysis of Temperature Variability on the Write Efficiency of Spin-Orbit Torque MRAM using Polynomial Chaos Metamodels.
ISQED
Sonal Shreya, Surila Guglani, Brajesh Kumar Kaushik, Sourajeet Roy
2017 J jnl
A Holistic Approach to Transforming Undergraduate Electrical Engineering Education.
IEEE Access
Anthony A. Maciejewski, Thomas W. Chen, Zinta S. Byrne, Michael A. De Miranda, Laura B. Sample Mcmeeking, Branislav M. Notaros, Ali Pezeshki, Sourajeet Roy, Andrea M. Leland, Melissa D. Reese, Alma H. Rosales, Thomas J. Siller, Richard F. Toftness, Olivera Notaros
2016 J jnl
Sparse Linear Regression (SPLINER) Approach for Efficient Multidimensional Uncertainty Quantification of High-Speed Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Majid Ahadi, Sourajeet Roy
2011 J jnl
Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations.
IEEE Trans. Very Large Scale Integr. Syst.
Sourajeet Roy, Anestis Dounavis
2011 J jnl
Transient Simulation of Distributed Networks Using Delay Extraction Based Numerical Convolution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sourajeet Roy, Anestis Dounavis
2009 J jnl
Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sourajeet Roy, Anestis Dounavis