Souradip Sarkar

11 papers A 1B 1C 3Journal 2Unranked 4
YearRankTypeTitle / Venue / Authors
2024 C conf
Agile Design-Space Exploration of Dynamic Layer-Skipping in Neural Receivers.
DSD
Bram Van Bolderik, Souradip Sarkar, Vlado Menkovski, Sonia M. Heemstra de Groot, Manil Dev Gomony
2019 C conf
A Reconfigurable Architecture for Posit Arithmetic.
DSD
Souradip Sarkar, Purushotham Murugappa, Manil Dev Gomony
2018 A conf
Quater-imaginary base for complex number arithmetic circuits.
DATE
Souradip Sarkar, Manil Dev Gomony
2018 — conf
Small Transactions with Sustainable Incentives.
NTMS
Fabio Pianese, Matteo Signorini, Souradip Sarkar
2012 J jnl
NoC-Based Hardware Accelerator for Breakpoint Phylogeny.
IEEE Trans. Computers
Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman
2012 B conf
Power-aware multi-core simulation for early design stage hardware/software co-optimization.
PACT
Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout
2011 — conf
Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era.
PARCO
Wim Heirman, Trevor E. Carlson, Souradip Sarkar, Pieter Ghysels, Wim Vanroose, Lieven Eeckhout
2010 — conf
An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem.
ASAP
Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman
2010 C conf
Hardware accelerators for biocomputing: A survey.
ISCAS
Souradip Sarkar, Turbo Majumder, Ananth Kalyanaraman, Partha Pratim Pande
2010 J jnl
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment.
IEEE Trans. Computers
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman
2007 — conf
Multiple clock domain synchronization for network on chip architectures.
SoCC
Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande