Soumya Pandit

21 papers A 1C 1Misc 3Journal 9Unranked 7
YearRankTypeTitle / Venue / Authors
2026 J jnl
Artificial intelligence in protein-based detection and inhibition of AMR pathways.
J. Comput. Aided Mol. Des.
Suchandrima Sadhukhan, Rupsa Bhattacharya, Debasmita Bhattcharya, Sudipta Sahana, Buddhadeb Pradhan, Soumya Pandit, Harjot Singh Gill, Mithul Rajeev, Moupriya Nag, Dibyajit Lahiri
2026 J jnl
Hardware-software codesign in an SoC-FPGA platform to implement a fusion framework using reduced dual-stack convolutional autoencoder.
Biomed. Signal Process. Control.
Arpita Das, Soumita Chatterjee, Shraman Biswas, Soumya Pandit
2025 J jnl
A 0.41-μW Self-Biased Temperature and Offset-Compensated Fully Differential Instrumentation Amplifier With 47 mdB/°C Thermal Sensitivity and 425 pVolt/°C Offset Drift.
Int. J. Circuit Theory Appl.
Koyel Mukherjee, Rajat Kumar Pal, Soumya Pandit
2025 J jnl
Coupling of a lightweight model of reduced convolutional autoencoder with linear SVM classifier to detect brain tumours on FPGA.
Expert Syst. Appl.
Soumita Chatterjee, Soumya Pandit, Arpita Das
2024 — conf
Design of A Custom IP Core for Concatenated SVM Model to Classify Multi-class Handwritten Numerical Characters.
VDAT
Shraman Biswas, Soumya Pandit, Arpita Das
2024 — conf
Design of FPGA based Custom IP Core to Detect the Edges of Brain Tumors.
VDAT
Soumita Chatterjee, Soumya Pandit, Arpita Das
2024 C conf
Machine Learning Algorithm for Handwritten Numerical Character Identification Using FPGA Based Custom IP Core.
TENCON
Shraman Biswas, Soumya Pandit, Arpita Das
2022 — conf
Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect.
VDAT
Subrata Das, Debesh Kumar Das, Soumya Pandit
2021 Misc conf
Minimization of Switching Activity of Graphene Based Circuits.
VLSID
Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das
2020 J jnl
A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects.
ACM J. Emerg. Technol. Comput. Syst.
Subrata Das, Debesh Kumar Das, Soumya Pandit
2019 — conf
FPGA Based Hardware Design for Noise Suppression and Seismic Event Detection.
iSES
Samik Basu, Soumya Pandit, Amlan Chakrabarti, Soma Barman Mandal
2014 — conf
Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications.
VDAT
Debayan Bairagi, Soumya Pandit
2013 — conf
An Improved
VDAT
Somnath Paul, Abhijit Dana, Soumya Pandit
2012 J jnl
Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics.
VLSI Design
Joyjit Mukhopadhyay, Soumya Pandit
2011 J jnl
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies.
VLSI Design
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
2011 Misc conf
Statistical Simulation and Modeling of Nano-scale CMOS VCO Using Artificial Neural Network.
VLSI Design
Sipra Mandal, Soumya Pandit
2010 J jnl
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator.
Integr.
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
2009 Misc conf
Systematic Methodology for High-Level Performance Modeling of Analog Systems.
VLSI Design
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
2008 J jnl
A Fast Exploration Procedure for Analog High-Level Specification Translation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra
2006 — conf
A formal approach for high level synthesis of linear analog systems.
ACM Great Lakes Symposium on VLSI
Soumya Pandit, Chittaranjan A. Mandal, Amit Patra
2006 A conf
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count.
DATE
Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra