Soumya Eachempati

12 papers A* 4A 1Journal 3Unranked 4

Year	Rank	Type	Title / Venue / Authors
2013	J	`jnl`	A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. ACM J. Emerg. Technol. Comput. Syst. Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan
2011	A*	`conf`	Automated mapping for reconfigurable single-electron transistor arrays. DAC Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan
2011	J	`jnl`	RAFT: A router architecture with frequency tuning for on-chip networks. J. Parallel Distributed Comput. Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2010	—	`conf`	Optimizing power and performance for reliable on-chip networks. ASP-DAC Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan
2009	A*	`conf`	A case for dynamic frequency tuning in on-chip networks. MICRO Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer, Narayanan Vijaykrishnan, Chita R. Das
2009	A*	`conf`	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. HPCA Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das
2009	—	`conf`	Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network. NANOARCH Yuan Xie, Soumya Eachempati, Aditya Yanamandra, Vijaykrishnan Narayanan, Mary Jane Irwin
2009	J	`jnl`	Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect. IET Circuits Devices Syst. Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud
2008	A*	`conf`	MIRA: A Multi-layered On-Chip Interconnect Router Architecture. ISCA Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das
2008	—	`conf`	Reconfigurable BDD based quantum circuits. NANOARCH Soumya Eachempati, Vinay Saripalli, Narayanan Vijaykrishnan, Suman Datta
2007	A	`conf`	Assessing carbon nanotube bundle interconnect for future FPGA architectures. DATE Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud
2007	—	`conf`	Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. ISVLSI Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud