Soumitra Kumar Nandy

16 papers A 1C 2Misc 6Journal 2Unranked 5
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures.
IEEE Commun. Surv. Tutorials
Oscar Ferraz, Srinivasan Subramaniyan, Ramesh Chinthala, João Andrade, Joseph R. Cavallaro, Soumitra Kumar Nandy, Vítor Silva, Xinmiao Zhang, Madhura Purnaprajna, Gabriel Falcão
2016 Misc conf
An Energy Efficient Dynamically Reconfigurable QR Decomposition for Wireless MIMO Communication.
VLSID
Ashish Kumar Pradhan, Soumitra Kumar Nandy
2016 Misc conf
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels.
VLSID
Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan
2016 Misc conf
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks.
VLSID
Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan
2015 — conf
An accelerator for classification using radial basis function neural network.
SoCC
Mahnaz Mohammadi, Rohit Ronge, Jayesh Ramesh Chandiramani, Soumitra Kumar Nandy
2011 — conf
Accelerating Reduction for Enabling Fast Multiplication over Large Binary Fields.
ICETE (Selected Papers)
Saptarsi Das, Ranjani Narayan, Soumitra Kumar Nandy
2011 J jnl
Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture.
IPSJ Trans. Syst. LSI Des. Methodol.
Ratna Krishnamoorthy, Saptarsi Das, Keshavan Varadarajan, Mythri Alle, Masahiro Fujita, Soumitra Kumar Nandy, Ranjani Narayan
2006 — conf
Efficient Key Management and Distribution for MANET.
ICC
Jayanta Biswas, Soumitra Kumar Nandy
2005 A conf
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer.
ITC
Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy
2004 — conf
Streaming stored playback video over a peer-to-peer network.
ICC
K. Kalapriya, K. Venkatesh Babu, Soumitra Kumar Nandy
2000 C conf
Controller redesign based clock and register power minimization.
ISCAS
Srikunth Rao M., Soumitra Kumar Nandy
2000 C conf
Performance evaluation of multithreaded architectures for media processing applications.
ISCAS
Srinivasan Balakrishnan, Soumitra Kumar Nandy
1998 Misc conf
Arbitrary Precision Arithmetic - SIMD Style.
VLSI Design
Srinivasan Balakrishnan, Soumitra Kumar Nandy
1997 — conf
An asynchronous architecture for digital signal processors.
ED&TC
M. R. Karthikeyan, Soumitra Kumar Nandy
1996 Misc conf
Spatial frequency based motion estimation for image sequence compression.
HiPC
Vinod Menezes, Soumitra Kumar Nandy, Biswadip Mitra
1995 Misc conf
Wave pipelined architecture folding: a method to achieve low power and low area.
VLSI Design
Debabrata Ghosh, Soumitra Kumar Nandy