Soumitra Bose - RankMe

25 papers A* 2A 8C 1Misc 3Journal 8Unranked 3

Year	Rank	Type	Title / Venue / Authors
2007	Misc	`conf`	Delay Test Quality Evaluation Using Bounded Gate Delays. VTS Soumitra Bose, Vishwani D. Agrawal
2007	A	`conf`	Delay fault simulation with bounded gate delay mode. ITC Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal
2007	A	`conf`	Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. ITC Soumitra Bose, Vishwani D. Agrawal
2006	A	`conf`	Fault Coverage Estimation for Non-Random Functional Input Sequences. ITC Soumitra Bose, Vishwani D. Agrawal
2006	Misc	`conf`	Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. VTS Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
2005	J	`jnl`	Schematic array models for associative and non-associative memory circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Soumitra Bose, Amit Nandi
2004	A	`conf`	Extraction of Schematic Array Models for Memory Circuits. DATE Soumitra Bose, Amit Nandi
2004	J	`jnl`	Modeling Custom Digital Circuits for Test. J. Electron. Test. Soumitra Bose
2002	A	`conf`	Automated Modeling of Custom Digital Circuits for Test. DATE Soumitra Bose
1998	J	`jnl`	A rated-clock test method for path delay faults. IEEE Trans. Very Large Scale Integr. Syst. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1998	J	`jnl`	Concurrent fault simulation on message passing multicomputers. IEEE Trans. Very Large Scale Integr. Syst. Soumitra Bose, Prathima Agrawal
1998	J	`jnl`	Deriving Logic Systems for Path Delay Test Generation. IEEE Trans. Computers Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1997	A	`conf`	Algorithms for Switch Level Delay Fault Simulation. ITC Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski
1995	—	`conf`	Sequential logic path delay test generation by symbolic analysis. Asian Test Symposium Soumitra Bose, Vishwani D. Agrawal
1993	Misc	`conf`	A Path Delay Fault Simulator for Sequential Circuits. VLSI Design Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	—	`conf`	Delay fault testability evaluation through timing simulation. Great Lakes Symposium on VLSI Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	A	`conf`	Generation of Compact Delay Tests by Multiple-Path Activation. ITC Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	—	`conf`	Logic systems for path delay test generation. EURO-DAC Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	J	`jnl`	Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1993	J	`jnl`	The optimistic update theorem for path delay testing in sequential circuits. J. Electron. Test. Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
1992	A*	`conf`	Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers. DAC Soumitra Bose, Prathima Agrawal
1992	J	`jnl`	PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. J. Autom. Reason. Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov
1989	A*	`conf`	PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses LICS Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov
1989	C	`conf`	Verifying pipelined hardware using symbolic logic simulation. ICCD Soumitra Bose, Allan L. Fisher
1988	A	`conf`	PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. CADE P. E. Allen, Soumitra Bose, Edmund M. Clarke, Spiro Michaylov