Sorin P. Voinigescu

70 papers C 1Journal 40Unranked 29

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	A Circuit Designer's Perspective on Transistor Modelling Challenges for 6G, Fiberoptics, and Quantum Computing ICs. BCICTS Sorin P. Voinigescu, Shai Bonen, Suyash Pati Tripathi, Saurabh Bagchi, Gregory Cooke, Thomas Jager, Akash Bharadwaj, Jessica Zhao
2023	—	`conf`	An 80-GBaud PAM-4 $G_{\mathrm{m}}$ -Boosted Variable-Gain TIA in 22-nm FDSOI. BCICTS Jianan Zhao, Sorin P. Voinigescu
2021	—	`conf`	200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator. ESSCIRC Naftali Weiss, Gregory Cooke, Peter Schvan, Pascal Chevalier, Andreia Cathelin, Sorin P. Voinigescu
2021	—	`conf`	Compact Modelling of 22nm FDSOI CMOS Semiconductor Quantum Dot Cryogenic I-V Characteristics. ESSCIRC Suyash Pati Tripathi, Shai Bonen, Claudia Nastase, Sergiu Iordanescu, George Boldeiu, Mircea Pasteanu, Alexandru Müller, Sorin P. Voinigescu
2021	—	`conf`	Compact Modelling of 22nm FDSOI CMOS Semiconductor Quantum Dot Cryogenic I-V Characteristics. ESSDERC Suyash Pati Tripathi, Shai Bonen, Claudia Nastase, Sergiu Iordanescu, George Boldeiu, Mircea Pasteanu, Alexandru Müller, Sorin P. Voinigescu
2019	—	`conf`	A 4.6V, 6-bit, 64GS/s Transmitter in 22nm FDSOI CMOS. BCICTS Jashva Rafique, The'Linh Nguyen, Sorin P. Voinigescu
2019	J	`jnl`	Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics Applications. IEEE J. Solid State Circuits Alireza Zandieh, Peter Schvan, Sorin P. Voinigescu
2018	—	`conf`	128-GS/s ADC Front-End with Over 60-GHz Input Bandwidth in 22-nm Si/SiGe FDSOI CMOS. BCICTS Alireza Zandieh, Naftali Weiss, The'Linh Nguyen, David Haranne, Sorin P. Voinigescu
2018	J	`jnl`	A IEEE J. Solid State Circuits Stefan Shopov, Ozan D. Gurbuz, Gabriel M. Rebeiz, Sorin P. Voinigescu
2018	—	`conf`	A 256-Gbps PAM-4 Signal Generator IC in 0.25-µm InP DHBT Technology. BCICTS Munehiko Nagatani, Hitoshi Wakita, Teruo Jyo, Miwa Mutoh, Minoru Ida, Sorin P. Voinigescu, Hideyuki Nosaka
2018	—	`conf`	A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications. BCICTS Alireza Zandieh, Peter Schvan, Sorin P. Voinigescu
2018	—	`conf`	Large-Swing 22nm Si/SiGe FDSOI Stacked Cascodes for 56GBaud Drivers and 5G PAs. BCICTS M. Sadeah Dadash, David Harame, Sorin P. Voinigescu
2018	—	`conf`	mm W and High Speed Solutions Enabled by FD-SOI. ESSCIRC Sorin P. Voinigescu
2018	—	`conf`	mmWand high speed solutions enabled by FD-SOI. ESSDERC Sorin P. Voinigescu
2017	—	`conf`	A 13.2-dBm, 138-GHz I/Q RF-DAC with 64-QAM and OFDM free-space constellation formation. ESSCIRC Stefan Shopov, Ozan D. Gurbuz, Gabriel M. Rebeiz, Sorin P. Voinigescu
2017	—	`conf`	A 44Gbps high extinction ratio silicon Mach-Zehnder modulator with a 3D-integrated 28nm FD-SOI CMOS driver. OFC Zheng Yong, Stefan Shopov, Jared C. Mikkelsen, Robert Mallard, Jason C. C. Mak, Sorin P. Voinigescu, Joyce K. S. Poon
2017	J	`jnl`	Introduction to the Special Section on the 2016 IEEE BCTM and IEEE CSICS. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Sorin P. Voinigescu
2017	J	`jnl`	SiGe HBT Technology: Future Trends and TCAD-Based Roadmap. Proc. IEEE Michael Schröter, Tommy Rosenbaum, Pascal Chevalier, Bernd Heinemann, Sorin P. Voinigescu, Ed Preisler, Josef Böck, Anindya Mukherjee
2017	J	`jnl`	Silicon Millimeter-Wave, Terahertz, and High-Speed Fiber-Optic Device and Benchmark Circuit Scaling Through the 2030 ITRS Horizon. Proc. IEEE Sorin P. Voinigescu, Stefan Shopov, James Bateman, Hassan Farooq, James Hoffman, Konstantinos Vasilakopoulos
2016	J	`jnl`	55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters. IEEE J. Solid State Circuits James Hoffman, Stefan Shopov, Pascal Chevalier, Andreia Cathelin, Peter Schvan, Sorin P. Voinigescu
2016	J	`jnl`	A 234-261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4-7.2 dBm Output Power, 1.3% DC-to-RF Efficiency, and 1-GHz Divided-Down Output. IEEE J. Solid State Circuits Stefan Shopov, Andreea Balteanu, Jürgen Hasch, Pascal Chevalier, Andreia Cathelin, Sorin P. Voinigescu
2016	J	`jnl`	A 3×60Gb/s Transmitter/Repeater Front-End With 4.3V IEEE J. Solid State Circuits Stefan Shopov, Sorin P. Voinigescu
2016	J	`jnl`	Analog Circuit Blocks for 80-GHz Bandwidth Frequency-Interleaved, Linear, Large-Swing Front-Ends. IEEE J. Solid State Circuits James Hoffman, Jean-Roland Martin-Gosse, Stefan Shopov, Jack J. Pekarik, Renata Camillo-Castillo, Vibhor Jain, David L. Harame, Sorin P. Voinigescu
2015	—	`conf`	A 3×40Gb/s 28nm FDSOI CMOS front-end array with 10mVPP sensitivity and >4VPP output swing. ESSCIRC Stefan Shopov, Sorin P. Voinigescu
2014	J	`jnl`	A 19 dBm, 15 Gbaud, 9 bit SOI CMOS Power-DAC Cell for High-Order QAM W-Band Transmitters. IEEE J. Solid State Circuits Stefan Shopov, Andreea Balteanu, Sorin P. Voinigescu
2014	J	`jnl`	A High Modulation Bandwidth, 110 GHz Power-DAC Cell for IQ Transmitter Arrays With Direct Amplitude and Phase Modulation. IEEE J. Solid State Circuits Andreea Balteanu, Stefan Shopov, Sorin P. Voinigescu
2013	—	`conf`	A 19-dBm, 15-Gbaud, 9-bit SOI CMOS power-DAC cell for high-order QAM W-band transmitters. ESSCIRC Stefan Shopov, Andreea Balteanu, Sorin P. Voinigescu
2013	J	`jnl`	A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters. IEEE J. Solid State Circuits Andreea Balteanu, Ioannis Sarkas, Eric Dacquay, Alexander Tomkins, Gabriel M. Rebeiz, Peter M. Asbeck, Sorin P. Voinigescu
2013	J	`jnl`	A Study of SiGe HBT Signal Sources in the 220-330-GHz Range. IEEE J. Solid State Circuits Sorin P. Voinigescu, Alexander Tomkins, Eric Dacquay, Pascal Chevalier, Jürgen Hasch, Alain Chantre, Bernard Sautreuil
2012	—	`conf`	A 45nm SOI CMOS Class-D mm-Wave PA with >10Vpp differential swing. ISSCC Ioannis Sarkas, Andreea Balteanu, Eric Dacquay, Alexander Tomkins, Sorin P. Voinigescu
2011	J	`jnl`	A 2.4-V IEEE J. Solid State Circuits Ricardo Andres Aroca, Peter Schvan, Sorin P. Voinigescu
2011	J	`jnl`	Design of a Dual W- and D-Band PLL. IEEE J. Solid State Circuits Shahriar Shahramian, Adam Hart, Alexander Tomkins, Anthony Chan Carusone, Patrice Garcia, Pascal Chevalier, Sorin P. Voinigescu
2010	J	`jnl`	A Passive W-Band Imaging Receiver in 65-nm Bulk CMOS. IEEE J. Solid State Circuits Alexander Tomkins, Patrice Garcia, Sorin P. Voinigescu
2010	J	`jnl`	An 18-Gb/s, Direct QPSK Modulation SiGe BiCMOS Transceiver for Last Mile Links in the 70-80 GHz Band. IEEE J. Solid State Circuits Ioannis Sarkas, Sean T. Nicolson, Alexander Tomkins, Ekaterina Laskin, Pascal Chevalier, Bernard Sautreuil, Sorin P. Voinigescu
2009	J	`jnl`	0.13µm SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications. IEEE J. Solid State Circuits Grégory Avenier, Malick Diop, Pascal Chevalier, Germaine Troillard, Nicolas Loubet, Julien Bouvier, Linda Depoyan, Nicolas Derrier, Michel Buczko, Cédric Leyris, Samuel Boret, Sébastien Montusclat, Alain Margain, Sébastien Pruvost, Sean T. Nicolson, Kenneth H. K. Yau, Nathalie Revil, Daniel Gloria, Didier Dutartre, Sorin P. Voinigescu, Alain Chantre
2009	J	`jnl`	A 1 GHz Bandwidth Low-Pass ΔΣADC With 20-50 GHz Adjustable Sampling Rate. IEEE J. Solid State Circuits Adam Hart, Sorin P. Voinigescu
2009	J	`jnl`	A 35-GS/s, 4-Bit Flash ADC With Active Data and Clock Distribution Trees. IEEE J. Solid State Circuits Shahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone
2009	J	`jnl`	A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link. IEEE J. Solid State Circuits Alexander Tomkins, Ricardo Andres Aroca, Takuji Yamamoto, Sean T. Nicolson, Yoshiyasu Doi, Sorin P. Voinigescu
2008	J	`jnl`	165-GHz Transceiver in SiGe Technology. IEEE J. Solid State Circuits Ekaterina Laskin, Pascal Chevalier, Alain Chantre, Bernard Sautreuil, Sorin P. Voinigescu
2008	—	`conf`	A 95GHz Receiver with Fundamental-Frequency VCO and Static Frequency Divider in 65nm Digital CMOS. ISSCC Ekaterina Laskin, Mehdi Khanpour, Ricardo Andres Aroca, Keith K. W. Tang, Patrice Garcia, Sorin P. Voinigescu
2008	J	`jnl`	A Large Swing, 40-Gb/s SiGe BiCMOS Driver With Adjustable Pre-Emphasis for Data Transmission Over 75Ω Coaxial Cable. IEEE J. Solid State Circuits Ricardo Andres Aroca, Sorin P. Voinigescu
2008	J	`jnl`	A Wideband W-Band Receiver Front-End in 65-nm CMOS. IEEE J. Solid State Circuits Mehdi Khanpour, Keith W. Tang, Patrice Garcia, Sorin P. Voinigescu
2008	—	`conf`	A zero-IF 60GHz transceiver in 65nm CMOS with ≫ 3.5Gb/s links. CICC Alexander Tomkins, Ricardo Andres Aroca, Takuji Yamamoto, Sean T. Nicolson, Yoshiyasu Doi, Sorin P. Voinigescu
2008	J	`jnl`	Single-Chip W-band SiGe HBT Transceivers and Receivers for Doppler Radar and Millimeter-Wave Imaging. IEEE J. Solid State Circuits Sean T. Nicolson, Pascal Chevalier, Bernard Sautreuil, Sorin P. Voinigescu
2008	—	`conf`	Will BiCMOS stay competitive for mmW applications ? CICC Patrice Garcia, Alain Chantre, Sébastien Pruvost, Pascal Chevalier, Sean T. Nicolson, David Roy, Sorin P. Voinigescu, Christophe Garnier
2007	—	`conf`	65-nm CMOS, W-Band Receivers for Imaging Applications. CICC Keith W. Tang, Mehdi Khanpour, Patrice Garcia, Christophe Gamier, Sorin P. Voinigescu
2007	J	`jnl`	A Low-Noise 40-GS/s Continuous-Time Bandpass ΔΣ ADC Centered at 2 GHz for Direct Sampling Receivers. IEEE J. Solid State Circuits Theodoros Chalvatzis, Eric Gagnon, Morris Repeta, Sorin P. Voinigescu
2007	J	`jnl`	Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio. IEEE J. Solid State Circuits Terry Yao, Michael Q. Gordon, Keith K. W. Tang, Kenneth H. K. Yau, Ming-Ta Yang, Peter Schvan, Sorin P. Voinigescu
2007	C	`conf`	CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples. ISCAS Sorin P. Voinigescu, Sean T. Nicolson, Mehdi Khanpour, Keith K. W. Tang, Kenneth H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, George V. Eleftheriades, Peter Schvan, Ming-Ta Yang
2007	J	`jnl`	Design and Scaling of W-Band SiGe BiCMOS VCOs. IEEE J. Solid State Circuits Sean T. Nicolson, Kenneth H. K. Yau, Pascal Chevalier, Alain Chantre, Bernard Sautreuil, Keith W. Tang, Sorin P. Voinigescu
2007	—	`conf`	Design for millimeter-wave applications in silicon technologies. ESSCIRC Andreia Cathelin, Baudouin Martineau, N. Seller, S. Douyere, Jean Gorisse, Sébastien Pruvost, Christine Raynaud, Frederic Gianesello, Sébastien Montusclat, Sorin P. Voinigescu, Ali M. Niknejad, Didier Belot, Jean-Pierre Schoellkopf
2007	J	`jnl`	Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS. IEEE J. Solid State Circuits Timothy O. Dickson, Sorin P. Voinigescu
2007	J	`jnl`	Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS. IEEE J. Solid State Circuits Theodoros Chalvatzis, Kenneth H. K. Yau, Ricardo Andres Aroca, Peter Schvan, Ming-Ta Yang, Sorin P. Voinigescu
2007	—	`conf`	Towards a sub-2.5V, 100-Gb/s Serial Transceiver. CICC Sorin P. Voinigescu, Ricardo Andres Aroca, Timothy O. Dickson, Sean T. Nicolson, Theodoros Chalvatzis, Pascal Chevalier, Patrice Garcia, Christophe Gamier, Bernard Sautreuil
2006	J	`jnl`	A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology. IEEE J. Solid State Circuits Adesh Garg, Anthony Chan Carusone, Sorin P. Voinigescu
2006	—	`conf`	A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology. CICC Shahriar Shahramian, Sorin P. Voinigescu, Anthony Chan Carusone
2006	J	`jnl`	A 60 mW per Lane, 4$, times, $23-Gb/s 2$ ^7 -$1 PRBS Generator. IEEE J. Solid State Circuits Ekaterina Laskin, Sorin P. Voinigescu
2006	J	`jnl`	Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology. IEEE J. Solid State Circuits Shahriar Shahramian, Anthony Chan Carusone, Sorin P. Voinigescu
2006	J	`jnl`	The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks. IEEE J. Solid State Circuits Timothy O. Dickson, Kenneth H. K. Yau, Theodoros Chalvatzis, Alain M. Mangan, Ekaterina Laskin, Rudy Beerkens, Paul Westergaard, Mihai Tazlauanu, Ming-Ta Yang, Sorin P. Voinigescu
2005	J	`jnl`	A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic. IEEE J. Solid State Circuits Timothy O. Dickson, Rudy Beerkens, Sorin P. Voinigescu
2005	—	`conf`	Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes. CICC Sorin P. Voinigescu, Timothy O. Dickson, Theodoros Chalvatzis, Altan Hazneci, Ekaterina Laskin, Rudy Beerkens, Imran Khalid, Edward S. Rogers Sr.
2005	J	`jnl`	An 80-Gb/s 2 IEEE J. Solid State Circuits Timothy O. Dickson, Ekaterina Laskin, Imran Khalid, Rudy Beerkens, Jingqiong Xie, Boris Karajica, Sorin P. Voinigescu
2005	—	`conf`	System-on-Chip Design beyond 50 GHz, invited. IWSOC Sorin P. Voinigescu, Michael Gordon, Chihou Lee, Terry Yao, Alain M. Mangan, Kenneth H. K. Yau
2004	J	`jnl`	6-kΩ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range. IEEE J. Solid State Circuits Hai Tran, Florin Pera, Douglas S. McPherson, Dorin Viorel, Sorin P. Voinigescu
2004	—	`conf`	A 1.5V 20/30 Gb/s CMOS backplane driver with digital pre-emphasis. CICC Paul Westergaard, Timothy O. Dickson, Sorin P. Voinigescu
2004	—	`conf`	An inductor-based 52-GHz 0.18 μm SiGe HBT cascode LNA with 22 dB gain. ESSCIRC Michael Gordon, Sorin P. Voinigescu
2004	J	`jnl`	Correction to "6-k$Omega$43-Gb/s Differential Transimpedance-Limiting Amplifier With Auto-Zero Feedback and High Dynamic Range". IEEE J. Solid State Circuits Hai Tran, FlorinPera Pera, Douglas S. McPherson, Dorin Viorel, Sorin P. Voinigescu
2003	J	`jnl`	A 3-V fully differential distributed limiting driver for 40-Gb/s optical transmission systems. IEEE J. Solid State Circuits Douglas S. McPherson, Florin Pera, Mihai Tazlauanu, Sorin P. Voinigescu
2001	—	`conf`	Circuits and technologies for highly integrated optical networking ICs at 10 Gb/s to 40 Gb/s. CICC Sorin P. Voinigescu, P. Popescu, P. Banens, Miles Copeland, G. Fortier, K. Howlett, M. Herod, David Marchesan, Jonathan L. Showell, S. Sziiagyi, Hai Tran, J. Weng
1997	J	`jnl`	A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. IEEE J. Solid State Circuits Sorin P. Voinigescu, Michael C. Maliepaard, Jonathan L. Showell, Greg E. Babcock, David Marchesan, Michael Schröter, Peter Schvan, David L. Harame