Sorin Dan Cotofana

70 papers A 5B 1C 17Journal 20Unranked 27

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Graphene-based, Frequency-Domain Self-Trigger for Low SNR Air Showers-induced Pulses. ISCAS Nicoleta Cucu Laurenciu, Charles Timmermans, Sorin Dan Cotofana
2024	C	`conf`	An Energy-Efficient Graphene-based Spiking Neural Network Architecture for Pattern Recognition. ISCAS Nicoleta Cucu Laurenciu, Charles Timmermans, Sorin Dan Cotofana
2024	J	`jnl`	CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network. IEEE Trans. Emerg. Top. Comput. Huiyi Gu, Xiaotao Jia, Yuhao Liu, Jianlei Yang, Xueyan Wang, Youguang Zhang, Sorin Dan Cotofana, Weisheng Zhao
2021	J	`jnl`	Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. IEEE Trans. Neural Networks Learn. Syst. Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
2020	J	`jnl`	Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. CoRR Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
2020	J	`jnl`	Reliability Aware Design and Lifetime Management of Computing Platforms. IEEE Trans. Emerg. Top. Comput. Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2020	C	`conf`	Ultra-Compact, Entirely Graphene-Based Nonlinear Leaky Integrate-and-Fire Spiking Neuron. ISCAS He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana
2019	C	`conf`	A Pragmatic Gaze on Stochastic Resonance Based Variability Tolerant Memristance Enhancement. ISCAS Vasileios G. Ntinas, Antonio Rubio, Georgios Ch. Sirakoulis, Sorin Dan Cotofana
2019	C	`conf`	Atomistic-Level Hysteresis-Aware Graphene Structures Electron Transport Model. ISCAS He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana
2019	—	`conf`	Graphene Nanoribbon-based Synapses with Versatile Plasticity. NANOARCH He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Dan Cotofana
2019	J	`jnl`	On Basic Boolean Function Graphene Nanoribbon Conductance Mapping. IEEE Trans. Circuits Syst. I Regul. Pap. Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2018	J	`jnl`	Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory. IEEE Trans. Emerg. Top. Comput. Marius Enachescu, Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana
2018	C	`conf`	On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps. ISCAS Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2017	—	`conf`	Fast and accurate workload-level neural network based IC energy consumption estimation. SMACD Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2017	—	`conf`	Haar-based interconnect coding for energy effective medium/long range data transport. SoCC Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2017	J	`jnl`	High-Performance, Cost-Effective 3D Stacked Wide-Operand Adders. IEEE Trans. Emerg. Top. Comput. George Razvan Voicu, Sorin Dan Cotofana
2017	C	`conf`	LDPC-Based Adaptive Multi-Error Correction for 3D Memories. ICCD Mihai Lefter, George Razvan Voicu, Thomas Marconi, Valentin Savin, Sorin Dan Cotofana
2017	—	`conf`	Low cost multi-error correction for 3D polyhedral memories. NANOARCH Mihai Lefter, Thomas Marconi, George Razvan Voicu, Sorin Dan Cotofana
2016	J	`jnl`	Brownian Circuits: Designs. Int. J. Unconv. Comput. Jia Lee, Ferdinand Peper, Sorin Dan Cotofana, Makoto Naruse, Motoichi Ohtsu, Tadashi Kawazoe, Yasuo Takahashi, Tetsuya Shimokawa, Laszlo B. Kish, Tohru Kubota
2016	—	`conf`	Error Correction Code protected Data Processing Units. NANOARCH Nicoleta Cucu Laurenciu, Tushar Gupta, Valentin Savin, Sorin Dan Cotofana
2015	C	`conf`	A shared polyhedral cache for 3D wide-I/O multi-core computing platforms. ISCAS Mihai Lefter, George Razvan Voicu, Sorin Dan Cotofana
2015	A	`conf`	Enabling vertical wormhole switching in 3D NoC-bus hybrid systems. DATE Changlin Chen, Marius Enachescu, Sorin Dan Cotofana
2015	C	`conf`	Low cost and energy, thermal noise driven, probability modulated random number generator. ISCAS Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2014	J	`jnl`	Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices. J. Parallel Distributed Comput. Yao Wang, Sorin Dan Cotofana, Liang Fang
2014	J	`jnl`	Critical transistors nexus based circuit-level aging assessment and prediction. J. Parallel Distributed Comput. Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2014	—	`conf`	Energy effective 3D stacked hybrid NEMFET-CMOS caches. NANOARCH Mihai Lefter, Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana
2014	—	`conf`	Towards an Effective Utilization of Partially Defected Interconnections in 2D Mesh NoCs. ISVLSI Changlin Chen, Sorin Dan Cotofana
2013	—	`conf`	3D stacked wide-operand adders: A case study. ASAP George Razvan Voicu, Mihai Lefter, Marius Enachescu, Sorin Dan Cotofana
2013	C	`conf`	A direct measurement scheme of amalgamated aging effects with novel on-chip sensor. VLSI-SoC Nicoleta Cucu Laurenciu, Yao Wang, Sorin Dan Cotofana
2013	—	`conf`	A low cost method to tolerate soft errors in the NoC router control plane. SoCC Changlin Chen, Sorin Dan Cotofana
2013	J	`jnl`	A nonlinear degradation path dependent end-of-life estimation framework from noisy observations. Microelectron. Reliab. Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2013	C	`conf`	An Effective Routing Algorithm to Avoid Unnecessary Link Abandon in 2D Mesh NoCs. DSD Changlin Chen, Sorin Dan Cotofana
2013	—	`conf`	An effective New CRT based reverse converter for a novel moduli set {2 ASAP Edem Kwedzo Bankas, Kazeem Alagbe Gbolagade, Sorin Dan Cotofana
2013	A	`conf`	Is TSV-based 3D integration suitable for inter-die memory repair? DATE Mihai Lefter, George Razvan Voicu, Mottaqiallah Taouil, Marius Enachescu, Said Hamdioui, Sorin Dan Cotofana
2013	—	`conf`	Lifetime reliability assessment with aging information from low-level sensors. ACM Great Lakes Symposium on VLSI Yao Wang, Sorin Dan Cotofana, Liang Fang
2013	—	`conf`	Towards heterogenous 3D-stacked reliable computing with von Neumann multiplexing. NANOARCH George Razvan Voicu, Sorin Dan Cotofana
2013	C	`conf`	Ultra low power NEMFET based logic. ISCAS Marius Enachescu, Mihai Lefter, Antonios Bazigos, Adrian M. Ionescu, Sorin Dan Cotofana
2012	C	`conf`	A 3D stacked high performance scalable architecture for 3D Fourier Transform. ICCD George Razvan Voicu, Marius Enachescu, Sorin Dan Cotofana
2012	—	`conf`	A Markovian, variation-aware circuit-level aging model. NANOARCH Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2012	—	`conf`	A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip. NOCS Changlin Chen, Ye Lu, Sorin Dan Cotofana
2012	J	`jnl`	Context aware slope based transistor-level aging model. Microelectron. Reliab. Nicoleta Cucu Laurenciu, Sorin Dan Cotofana
2012	C	`conf`	Is the road towards "Zero-Energy" paved with NEMFET-based power management? ISCAS Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana
2012	—	`conf`	Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices. NANOARCH Yao Wang, Sorin Dan Cotofana, Liang Fang
2012	J	`jnl`	Variation tolerant on-chip degradation sensors for dynamic reliability management systems. Microelectron. Reliab. Yao Wang, Marius Enachescu, Sorin Dan Cotofana, Liang Fang
2012	—	`conf`	Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits. NANOARCH Saleh Safiruddin, Mihai Lefter, Demid Borodin, George Razvan Voicu, Sorin Dan Cotofana
2011	J	`jnl`	An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set 2n+1, 2n, 2n-1. IEEE Trans. Very Large Scale Integr. Syst. Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana
2011	C	`conf`	Analysis of delay mismatching of digital circuits caused by common environmental fluctuations. ISCAS Dennis Andrade, Antonio Rubio, Antonio Calomarde, Sorin Dan Cotofana
2011	—	`conf`	Functional unit sharing between stacked processors in 3D integrated systems. ICSAMOS Demid Borodin, Winston Siauw, Sorin Dan Cotofana
2011	—	`conf`	Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs. NANOARCH George Razvan Voicu, Marius Enachescu, Sorin Dan Cotofana
2010	C	`conf`	A unified addition structure for moduli set {2 ICCD Somayeh Timarchi, Mahmood Fazlali, Sorin Dan Cotofana
2010	C	`conf`	An improved RNS reverse converter for the {2 ISCAS Kazeem Alagbe Gbolagade, Ricardo Chaves, Leonel Sousa, Sorin Dan Cotofana
2010	—	`conf`	Memoryless RNS-to-binary converters for the {2 ASAP Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana
2009	—	`conf`	A reverse converter for the new 4-moduli set {2n + 3, 2n + 2, 2n + 1, 2n}. ICECS Kazeem Alagbe Gbolagade, Sorin Dan Cotofana
2008	—	`conf`	A residue to binary converter for the {2n + 2, 2n + 1, 2n} moduli set. ACSCC Kazeem Alagbe Gbolagade, Sorin Dan Cotofana
2008	B	`conf`	Bitstream compression techniques for Virtex 4 FPGAs. FPL Radu Andrei Stefan, Sorin Dan Cotofana
2008	A	`conf`	Compositional, dynamic cache management for embedded chip multiprocessors. DATE Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana
2008	—	`conf`	Generalized matrix method for efficient residue to decimal conversion. APCCAS Kazeem Alagbe Gbolagade, Sorin Dan Cotofana
2008	—	`conf`	Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits. NANOARCH Saleh Safiruddin, Sorin Dan Cotofana, Ferdinand Peper
2007	J	`jnl`	Compositional Memory Systems for Multimedia Communicating Tasks CoRR Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
2007	J	`jnl`	Static Cache Partitioning Robustness Analysis for Embedded On-Chip Multi-processors. Trans. High Perform. Embed. Archit. Compil. Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
2006	A	`conf`	Compositional, efficient caches for a chip multi-processor. DATE Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
2006	—	`conf`	Static cache partitioning robustness analysis for embedded on-chip multi-processors. Conf. Computing Frontiers Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
2006	—	`conf`	Throughput optimization via cache partitioning for embedded multiprocessors. ICSAMOS Anca Mariana Molnos, Sorin Dan Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
2005	J	`jnl`	Addition Related Arithmetic Operations via Controlled Transport of Charge. IEEE Trans. Computers Sorin Dan Cotofana, Casper Lageweg, Stamatis Vassiliadis
2005	A	`conf`	Compositional Memory Systems for Multimedia Communicating Tasks. DATE Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Dan Cotofana, Jos T. J. van Eijndhoven
2004	J	`jnl`	Analog-to-digital converter based on single-electron tunneling transistors. IEEE Trans. Very Large Scale Integr. Syst. Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang, Qiyu Cai
2004	—	`conf`	Analysis of analog to digital converter based on single-electron tunnelling transistors. ISCAS (3) Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang
2004	J	`jnl`	Pel reconstruction on FPGA-augmented TriMedia. IEEE Trans. Very Large Scale Integr. Syst. Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2004	J	`jnl`	Single-electron tunneling transistor implementation of periodic symmetric functions. IEEE Trans. Circuits Syst. II Express Briefs Chaohong Hu, Sorin Dan Cotofana, Jianfei Jiang
2003	—	`conf`	Area efficient, high speed parallel counter circuits using charge recycling threshold logic. ISCAS (5) Peter Celinski, Derek Abbott, Sorin Dan Cotofana