Sorin Cotofana

108 papers A 8B 3C 15Misc 2Journal 26Unranked 53
YearRankTypeTitle / Venue / Authors
2025 C conf
A Convoluted Journey from CMOS to Spin Waves.
ISCAS
Pantazis Anagnostou, Arne Van Zegbroeck, Said Hamdioui, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana
2025 J jnl
Benchmarking of Scaled Majority-Logic-Synthesized Spintronic Circuits Based on Magnetic Tunnel Junction Transducers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fanfan Meng, Siang-Yun Lee, Odysseas Zografos, Mohit Gupta, Van D. Nguyen, Giovanni De Micheli, Sorin Cotofana, Inge Asselberghs, Christoph Adelmann, Gouri Sankar Kar, Sebastien Couet, Florin Ciubotaru
2024 J jnl
An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method.
IEEE Trans. Neural Networks Learn. Syst.
Xiaotao Jia, Huiyi Gu, Yuhao Liu, Jianlei Yang, Xueyan Wang, Weitao Pan, Youguang Zhang, Sorin Cotofana, Weisheng Zhao
2024 J jnl
Spin Wave Threshold Gate.
CoRR
Arne Van Zegbroeck, Pantazis Anagnostou, Said Hamdioui, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana
2024 J jnl
Spintronic logic: from transducers to logic gates and circuits.
CoRR
Christoph Adelmann, Florin Ciubotaru, Fanfan Meng, Sorin Cotofana, Sebastien Couet
2024 J jnl
Two Cascaded Spin Wave Majority Gates Operation Under Continuous and Pulse Modes.
IEEE Trans. Circuits Syst. II Express Briefs
Abdulqader Nael Mahmoud, Florin Ciubotaru, Frederic Vanderveken, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
2023 J jnl
Roadmap for Unconventional Computing with Nanotechnology.
CoRR
Giovanni Finocchio, Supriyo Bandyopadhyay, Peng Lin, Gang Pan, J. Joshua Yang, Riccardo Tomasello, Christos Panagopoulos, Mario Carpentieri, Vito Puliafito, Johan Åkerman, Hiroki Takesue, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Kaushik Roy, Vinod K. Sangwan, Mark C. Hersam, Anna Giordano, Huynsoo Yang, Julie Grollier, Kerem Yunus Çamsari, Peter L. McMahon, Supriyo Datta, Jean Anne C. Incorvia, Joseph S. Friedman, Sorin Cotofana, Florin Ciubotaru, Andrii V. Chumak, Azad J. Naeemi, Brajesh Kumar Kaushik, Yao Zhu, Wang Kang, Belita Koiller, Gabriel Aguilar, Guilherme P. Temporão, Kremena Makasheva, Aida Todri-Sanial, Jennifer Hasler, William Levy, Vwani Roychowdhury, Samiran Ganguly, Avik W. Ghosh, Davi Rodriquez, Satoshi Sunada, Karin Everschor-Sitte, Amit Lal, Shubham Jadhav, Massimiliano Di Ventra, Yuriy V. Pershin, Kosuke Tatsumura, Hayato Goto
2023 — conf
Spin Wave Threshold Logic Gates.
NANOARCH
Arne Van Zegbroeck, Pantazis Anagnostou, Said Hamdioui, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana
2022 J jnl
Non-Binary Spin Wave Based Circuit Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Said Hamdioui, Sorin Cotofana
2022 J jnl
Spin Wave Based Approximate Computing.
IEEE Trans. Emerg. Top. Comput.
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Said Hamdioui, Sorin Cotofana
2022 — conf
Would Magnonic Circuits Outperform CMOS Counterparts?
ACM Great Lakes Symposium on VLSI
Abdulqader Nael Mahmoud, Nicoleta Cucu Laurenciu, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
2021 — conf
Achieving Wave Pipelining in Spin Wave Technology.
ISQED
Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana
2021 A conf
Fan-out of 2 Triangle Shape Spin Wave Logic Gates.
DATE
Abdulqader Nael Mahmoud, Christoph Adelmann, Frederic Vanderveken, Sorin Cotofana, Florin Ciubotaru, Said Hamdioui
2021 J jnl
Graphene-Based Artificial Synapses with Tunable Plasticity.
ACM J. Emerg. Technol. Comput. Syst.
He Wang, Nicoleta Cucu Laurenciu, Yande Jiang, Sorin Cotofana
2021 — conf
Spin Wave Based 4-2 Compressor.
ICECS
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
2021 C conf
Spin Wave Based Full Adder.
ISCAS
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
2021 J jnl
Spin Wave Normalization Toward All Magnonic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana, Said Hamdioui
2020 — conf
2-Output Spin Wave Programmable Logic Gate.
ISVLSI
Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana, Said Hamdioui
2020 C conf
4-output Programmable Spin Wave Logic Gate.
ICCD
Abdulqader Nael Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Said Hamdioui, Sorin Cotofana
2020 J jnl
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM.
IEEE Trans. Circuits Syst.
Jinkai Wang, Chenyu Lian, Yining Bai, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Lei Chen, Kelian Lin, Kun Zhang, Youguang Zhang, Xiulong Wu, Sorin Cotofana, Yue Zhang
2020 J jnl
Evolutionary Bin Packing for Memory-Efficient Dataflow Inference Acceleration on FPGA.
CoRR
Mairin Kroes, Lucian Petrica, Sorin Cotofana, Michaela Blott
2020 A conf
Evolutionary bin packing for memory-efficient dataflow inference acceleration on FPGA.
GECCO
Mairin Kroes, Lucian Petrica, Sorin Cotofana, Michaela Blott
2020 — conf
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA.
FPT
Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott
2020 J jnl
Memory-Efficient Dataflow Inference for Deep CNNs on FPGA.
CoRR
Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas J. Fraser, Sorin Cotofana, Michaela Blott
2020 C conf
Memristive Oscillatory Circuits for Resolution of NP-Complete Logic Puzzles: Sudoku Case.
ISCAS
Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis
2020 J jnl
Memristive oscillatory circuits for resolution of NP-complete logic puzzles: Sudoku case.
CoRR
Theodoros Panagiotis Chatzinikolaou, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vasileios G. Ntinas, Giorgos Dimitrakopoulos, Sorin Cotofana, Georgios Ch. Sirakoulis
2020 A conf
n-bit Data Parallel Spin Wave Logic Gate.
DATE
Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui
2018 — conf
Complementary Arranged Graphene Nanoribbon-based Boolean Gates.
NANOARCH
Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Cotofana
2017 — conf
A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance.
ACM Great Lakes Symposium on VLSI
Xu He, Yao Wang, Yang Guo, Sorin Cotofana
2017 J jnl
Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Changlin Chen, Yaowen Fu, Sorin Cotofana
2016 — conf
A supply voltage-dependent variation aware reliability evaluation model.
NANOARCH
Bo Yang, Emanuel M. Popovici, Michael Alan Quille, Andreas Amann, Sorin Cotofana
2016 C conf
Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders with Fully-Parallel Processing Units.
DSD
Thien Truong Nguyen-Ly, Tushar Gupta, Manuel Pezzin, Valentin Savin, David Declercq, Sorin Cotofana
2016 — conf
TFET NDR skewed inverter based sensing method.
NANOARCH
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Sorin Cotofana, Costin Anghel
2015 — conf
Asynchronous Charge Sharing Power Consistent Montgomery Multiplier.
ASYNC
Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana
2015 — conf
Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding.
ACM Great Lakes Symposium on VLSI
Thomas Marconi, Sorin Cotofana
2015 A conf
Hybrid adaptive clock management for FPGA processor acceleration.
DATE
Alexandru Gheolbanoiu, Lucian Petrica, Sorin Cotofana
2015 J jnl
Inverse Gaussian distribution based timing analysis of Sub-threshold CMOS circuits.
Microelectron. Reliab.
Jiaoyan Chen, Sorin Cotofana, Satish Grandhi, Christian Spagnol, Emanuel M. Popovici
2015 C conf
ROST-C: Reliability driven optimisation and synthesis techniques for combinational circuits.
ICCD
Satish Grandhi, David McCarthy, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana
2014 — conf
An efficient residue-to-binary converter for the new moduli set {2
ISIC
Hillary Siewobr, Kazeem Alagbe Gbolagade, Sorin Cotofana
2014 J jnl
Efficient Method for Designing Modulo {2
J. Circuits Syst. Comput.
Héctor Pettenghi, Sorin Cotofana, Leonel Sousa
2014 — ed.
IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014, Paris, France, July 8-10, 2014
NANOARCH
Jacques-Olivier Klein, Csaba Andras Moritz, Sorin Cotofana
2014 — conf
Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits.
ISVLSI
Jiaoyan Chen, Christian Spagnol, Satish Grandhi, Emanuel M. Popovici, Sorin Cotofana, Alexandru Amaricai
2014 — conf
Link Bandwidth Aware Backtracking Based Dynamic Task Mapping in NoC based MPSoCs.
NoCArc@MICRO
Changlin Chen, Sorin Cotofana
2014 — conf
Robust sub-powered asynchronous logic.
PATMOS
Jiaoyan Chen, Arnaud Tisserand, Emanuel M. Popovici, Sorin Cotofana
2014 C conf
Towards energy effective LDPC decoding by exploiting channel noise variability.
VLSI-SoC
Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana
2014 — conf
Transmission Channel Noise Aware Energy Effective LDPC Decoding.
VLSI-SoC (Selected Papers)
Thomas Marconi, Christian Spagnol, Emanuel M. Popovici, Sorin Cotofana
2012 — conf
Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms.
Map2MPSoC/SCOPES
Anca Mariana Molnos, Ashkan Beyranvand Nejad, Ba Thang Nguyen, Sorin Cotofana, Kees Goossens
2012 — conf
Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints.
WESE
Andrew Nelson, Anca Molnos, Ashkan Beyranvand Nejad, Davit Mirzoyan, Sorin Cotofana, Kees Goossens
2012 — conf
Stigmergic search with single electron tunneling technology based memory enhanced hubs.
NANOARCH
Saleh Safiruddin, Sorin Cotofana, Ferdinand Peper
2011 — conf
A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits.
NANOARCH
Yao Wang, Sorin Cotofana, Liang Fang
2011 — conf
Composable local memory organisation for streaming applications on embedded MPSoCs.
Conf. Computing Frontiers
Jude Angelo Ambrose, Anca Mariana Molnos, Andrew Nelson, Sorin Cotofana, Kees Goossens, Ben H. H. Juurlink
2009 — conf
Adaptive Clock Scheduling for pipelined structures.
NANOARCH
Ben Kuiper, Sorin Cotofana
2009 C conf
An O(n) Residue Number System to Mixed Radix Conversion Technique.
ISCAS
Kazeem Alagbe Gbolagade, Sorin Cotofana
2009 — conf
Can SG-FET Replace FET in Sleep Mode Circuits?
NanoNet
Marius Enachescu, Sorin Cotofana, Arjan J. van Genderen, Dimitrios Tsamados, Adrian M. Ionescu
2009 J jnl
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors.
J. Signal Process. Syst.
Anca Mariana Molnos, Sorin Cotofana, Marc J. M. Heijligers, Jos T. J. van Eijndhoven
2009 — conf
Emerging non-CMOS nanoelectronic devices - What are they?.
NEMS
Nor Zaidi Haron, Said Hamdioui, Sorin Cotofana
2008 J jnl
GRAAL: A Framework for Low-Power 3D Graphics Accelerators.
IEEE Computer Graphics and Applications
Ben H. H. Juurlink, Iosif Antochi, Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis
2006 — conf
Consciousness for modeling intelligence - simulating the evolution by closure to the inverse.
ICINCO-ICSO
Tudor Niculiu, Cristian Lupu, Sorin Cotofana
2006 C conf
Electron counting based high-radix multiplication in single electron tunneling technology.
ISCAS
Cor Meenderinck, Sorin Cotofana
2006 — conf
High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology.
SAMOS
Cor Meenderinck, Sorin Cotofana
2005 — conf
CONAN - A Design Exploration Framework for Reliable Nano-Electronics.
ASAP
Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio
2005 — conf
High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology.
ASAP
Cor Meenderinck, Sorin Cotofana, Casper Lageweg
2005 J jnl
IEEE-Compliant IDCT on FPGA-Augmented TriMedia.
J. VLSI Signal Process.
Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers
2004 — conf
Binary Multiplication based on Single Electron Tunneling.
ASAP
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
2004 A conf
Compositional Memory Systems for Data Intensive Applications.
DATE
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin Cotofana, Jos T. J. van Eijndhoven
2004 — conf
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic.
PATMOS
Peter Celinski, Derek Abbott, Sorin Cotofana
2004 C conf
Efficient Hardware for Antialiasing Coverage Mask Generation.
Computer Graphics International
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
2004 A conf
GRAAL - A Development Framework for Embedded Graphics Accelerators.
DATE
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
2004 — conf
High-Level Energy Estimation for ARM-Based SOCs.
SAMOS
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha
2004 — conf
Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach.
ISVLSI
Peter Celinski, Said F. Al-Sarawi, Derek Abbott, Sorin Cotofana, Stamatis Vassiliadis
2004 — conf
Low cost and latency embedded 3D graphics reciprocation.
ISCAS (2)
Dan Crisu, Stamatis Vassiliadis, Sorin Cotofana, Petri Liuha
2003 A conf
A Hierarchical Sparse Matrix Storage Format for Vector Processors.
IPDPS
Pyrrhos Stathis, Stamatis Vassiliadis, Sorin Cotofana
2003 — conf
A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder.
IWANN (2)
Peter Celinski, Sorin Cotofana, Derek Abbott
2003 — conf
CMOS Implementation of Generalized Threshold Functions.
IWANN (2)
Marius Padure, Sorin Cotofana, Stamatis Vassiliadis
2003 — conf
Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor.
ASAP
Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven
2003 B conf
D-SAB: A Sparse Matrix Benchmark Suite.
PaCT
Pyrrhos Stathis, Stamatis Vassiliadis, Sorin Cotofana
2003 — conf
Design and experimental results of a CMOS flip-flop featuring embedded threshold logic.
ISCAS (5)
Marius Padure, Sorin Cotofana, Stamatis Vassiliadis
2003 C conf
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.
VLSI-SOC
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
2003 — conf
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.
VLSI-SoC (Selected Papers)
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
2003 J jnl
Microcode Processing: Positioning and Directions.
IEEE Micro
Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana
2003 C conf
On Computing Addition Related Arithmetic Operations via Controlled Transport of Charge.
IEEE Symposium on Computer Arithmetic
Sorin Cotofana, Casper Lageweg, Stamatis Vassiliadis
2002 — conf
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.
Embedded Processor Design Challenges
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2002 — conf
A Sum of Absolute Differences Implementation in FPGA Hardware.
EUROMICRO
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
2002 — conf
A full adder implementation using SET based linear threshold gates.
ICECS
Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis
2002 — conf
A low-power threshold logic family.
ICECS
Marius Padure, Sorin Cotofana, Stamatis Vassiliadis, Claudius Dan, Mircea Bodea
2002 — conf
Alternatives in FPGA-based SAD implementations.
FPT
Stephan Wong, Bastiaan Stougie, Sorin Cotofana
2002 B conf
Field-Programmable Custom Computing Machines - A Taxonomy -.
FPL
Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T. J. van Eijndhoven, Kees A. Vissers
2002 — conf
Hierarchical Intellignet Mixed Simulation.
ESM
Tudor Niculiu, Sorin Cotofana
2002 Misc conf
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64.
FCCM
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2002 — conf
Microcoded Reconfigurable Embedded Processors: Current Developments.
Embedded Processor Design Challenges
Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana
2001 Misc conf
An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia.
FCCM
Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers
2001 C conf
Coarse Reconfigurable Multimedia Unit Extension.
PDP
Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
2001 C conf
MPEG Macroblock Parsing and Pel Reconstruction On An FPGA-Augmented TriMedia Processor.
ICCD
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
2001 B conf
The MOLEN rho-mu-Coded Processor.
FPL
Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana
2001 — conf
Topic 15+20: Multimedia and Embedded Systems.
Euro-Par
Stamatis Vassiliadis, Francky Catthoor, Mateo Valero, Sorin Cotofana
2000 — conf
Counter Based Superscalar Instruction Issuing.
EUROMICRO
Sorin Cotofana, Ben H. H. Juurlink, Stamatis Vassiliadis
2000 — conf
General-Purpose Processor Huffman Encoding Extension.
ITCC
Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
2000 — conf
Hashed Addressed Caches for Embedded Pointer Based Codes (Research Note).
Euro-Par
Marian Stanca, Stamatis Vassiliadis, Sorin Cotofana, Henk Corporaal
2000 — conf
Hierarchical interfaces for hardware software systems.
ESM
Tudor Niculiu, Chouki Aktouf, Sorin Cotofana
2000 A conf
Multimedia Enhanced General-Purpose Processors.
IEEE International Conference on Multimedia and Expo (III)
Stephan Wong, Sorin Cotofana, Stamatis Vassiliadis
2000 J jnl
Signed Digit Addition and Related Operations with Threshold Logic.
IEEE Trans. Computers
Sorin Cotofana, Stamatis Vassiliadis
1999 J jnl
Serial binary multiplication with feed-forward neural networks.
Neurocomputing
Sorin Cotofana, Stamatis Vassiliadis
1999 — conf
Vector ISA Extension for Sparse Matrix-Vector Multiplication.
Euro-Par
Stamatis Vassiliadis, Sorin Cotofana, Pyrrhos Stathis
1998 — conf
On the Design Complexity of the Issue Logic of Superscalar Machines.
EUROMICRO
Sorin Cotofana, Stamatis Vassiliadis
1998 J jnl
Periodic symmetric functions, serial addition, and multiplication with neural networks.
IEEE Trans. Neural Networks
Sorin Cotofana, Stamatis Vassiliadis
1996 J jnl
2-1 Additions and Related Arithmetic Operations with Threshold Logic.
IEEE Trans. Computers
Stamatis Vassiliadis, Sorin Cotofana, Koen Bertels
1996 C conf
Serial Binary Addition with Polynominally Bounded Weights.
ICANN
Sorin Cotofana, Stamatis Vassiliadis
1996 J jnl
delta-Bit serial binary addition with linear threshold networks.
J. VLSI Signal Process.
Sorin Cotofana, Stamatis Vassiliadis