Soontae Kim - RankMe

88 papers A* 6A 16B 3C 7Misc 2Journal 46Unranked 8

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Path Tracking Controller for Heavy-Duty Buses Based on Robust Model Predictive Control With a Novel Enhanced Kinematic Model. IEEE Trans. Intell. Veh. Sangwon Han, Yuho Song, Soontae Kim, Kunsoo Huh
2025	A	`conf`	C2C: A Framework for Critical Token Classification in Transformer-Based Inference Systems. DATE Myeongjae Jang, Jesung Kim, Haejin Nam, Sihyun Kim, Soontae Kim
2025	J	`jnl`	Enhancing Rule-Based Hands-Off Detection With Deep Learning and Permutation Feature Analysis. IEEE Trans. Intell. Veh. Soontae Kim, Kunsoo Huh
2025	J	`jnl`	Real-Time Long Horizon Air Quality Forecasting via Group-Relative Policy Optimization. CoRR Inha Kang, Eunki Kim, Wonjeong Ryu, Jaeyo Shin, Seungjun Yu, Yoon-Hee Kang, Seongeun Jeong, Eunhye Kim, Soontae Kim, Hyunjung Shim
2024	J	`jnl`	Highly VM-Scalable SSD in Cloud Storage Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wonyoung Lee, Mincheol Kang, Soontae Kim
2024	J	`jnl`	Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural Networks. IEEE Trans. Computers Myeongjae Jang, Jinkwon Kim, Haejin Nam, Soontae Kim
2023	J	`jnl`	Effective Emoticon Suggestion Technique Based on Active Emotional Input Using Facial Expressions and Heart Rate Signals. Sensors Jesung Kim, Mincheol Kang, Bohun Seo, Jeongkyu Hong, Soontae Kim
2023	—	`conf`	Estimated State-Based Optimal Path Planning and Control System for Lane-Keeping of Semi-Trailer Trucks. ITSC Sangwon Han, Geonyeong Park, Yoonyong Ahn, Gunhee Cho, Soontae Kim, Kunsoo Huh
2023	A*	`conf`	HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator. MICRO Jinkwon Kim, Myeongjae Jang, Haejin Nam, Soontae Kim
2023	J	`jnl`	PR-SSD: Maximizing Partial Read Potential by Exploiting Compression and Channel-Level Parallelism. IEEE Trans. Computers Mincheol Kang, Wonyoung Lee, Jinkwon Kim, Soontae Kim
2022	A	`conf`	ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks. DATE Myeongjae Jang, Jinkwon Kim, Jesung Kim, Soontae Kim
2022	J	`jnl`	Efficient Integrity-Tree Structure for Convolutional Neural Networks through Frequent Counter Overflow Prevention in Secure Memories. Sensors Jesung Kim, Wonyoung Lee, Jeongkyu Hong, Soontae Kim
2022	A*	`conf`	Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data. HPCA Jinkwon Kim, Mincheol Kang, Jeongkyu Hong, Soontae Kim
2022	A	`conf`	Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD Performance. DATE Junoh Moon, Mincheol Kang, Wonyoung Lee, Soontae Kim
2021	J	`jnl`	CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems. IEEE Trans. Computers Jinkwon Kim, Seokin Hong, Jeongkyu Hong, Soontae Kim
2021	J	`jnl`	ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories. IEEE Trans. Computers Hamed Farbeh, Leila Delshadtehrani, Hyeonggyu Kim, Soontae Kim
2021	J	`jnl`	Update Frequency-Directed Subpage Management for Mitigating Garbage Collection and DRAM Overheads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Imran Fareed, Mincheol Kang, Wonyoung Lee, Soontae Kim
2020	J	`jnl`	Freezing: Eliminating Unnecessary Drawing Computation for Low Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bohun Seo, Hyeonggyu Kim, Soontae Kim
2020	A	`conf`	Leveraging intra-page update diversity for mitigating write amplification in SSDs. ICS Imran Fareed, Mincheol Kang, Wonyoung Lee, Soontae Kim
2020	J	`jnl`	SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches. IEEE Trans. Very Large Scale Integr. Syst. Muhammad Avais Qureshi, Jungwoo Park, Soontae Kim
2019	J	`jnl`	A Restore-Free Mode for MLC STT-RAM Caches. IEEE Trans. Very Large Scale Integr. Syst. Muhammad Avais Qureshi, Hyeonggyu Kim, Soontae Kim
2019	J	`jnl`	Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages. IEEE Trans. Very Large Scale Integr. Syst. Wonyoung Lee, Mincheol Kang, Seokin Hong, Soontae Kim
2019	J	`jnl`	MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems. ACM Trans. Archit. Code Optim. Jungwoo Park, Myoungjun Lee, Soontae Kim, Minho Ju, Jeongkyu Hong
2019	J	`jnl`	Time-sensitivity-aware shared cache architecture for multi-core embedded systems. J. Supercomput. Myoungjun Lee, Soontae Kim
2018	B	`conf`	EAR: ECC-aided refresh reduction through 2-D zero compression. PACT Jeongkyu Hong, Hyeonggyu Kim, Soontae Kim
2018	J	`jnl`	OnNetwork+: Network Delay-Aware Management for Mobile Systems. ACM Trans. Embed. Comput. Syst. Hyeonggyu Kim, Minho Ju, Soontae Kim
2018	J	`jnl`	Subpage-Aware Solid State Drive for Improving Lifetime and Performance. IEEE Trans. Computers Mincheol Kang, Wonyoung Lee, Soontae Kim
2017	J	`jnl`	A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption. IEEE Trans. Very Large Scale Integr. Syst. Jungwoo Park, Jongmin Lee, Soontae Kim
2017	A*	`conf`	Partial Row Activation for Low-Power DRAM System. HPCA Yebin Lee, Hyeonggyu Kim, Seokin Hong, Soontae Kim
2017	J	`jnl`	Smart ECC Allocation Cache Utilizing Cache Data Space. IEEE Trans. Computers Jeongkyu Hong, Soontae Kim
2017	J	`jnl`	TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption. IEEE Trans. Computers Jesung Kim, Jongmin Lee, Soontae Kim
2017	J	`jnl`	Write-Amount-Aware Management Policies for STT-RAM Caches. IEEE Trans. Very Large Scale Integr. Syst. Hyeonggyu Kim, Soontae Kim, Jooheung Lee
2016	J	`jnl`	CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System. IEEE Trans. Very Large Scale Integr. Syst. Yebin Lee, Soontae Kim
2016	J	`jnl`	Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures. IEEE Trans. Computers Seokin Hong, Soontae Kim
2016	J	`jnl`	Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches. IEEE Trans. Very Large Scale Integr. Syst. Jeongkyu Hong, Soontae Kim
2016	J	`jnl`	Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches. IEEE Trans. Computers Hamed Farbeh, Hyeonggyu Kim, Seyed Ghassem Miremadi, Soontae Kim
2016	B	`conf`	MofySim: A mobile full-system simulation framework for energy consumption and performance analysis. ISPASS Minho Ju, Hyeonggyu Kim, Soontae Kim
2016	A	`conf`	Network delay-aware energy management for mobile systems. DATE Minho Ju, Hyeonggyu Kim, Soontae Kim
2016	J	`jnl`	RAMS: DRAM Rank-Aware Memory Scheduling for Energy Saving. IEEE Trans. Computers Yebin Lee, Soontae Kim
2016	J	`jnl`	Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. Jongmin Lee, Soontae Kim
2015	J	`jnl`	A Low-Cost Mechanism Exploiting Narrow-Width Values for Tolerating Hard Faults in ALU. IEEE Trans. Computers Seokin Hong, Soontae Kim
2015	—	`conf`	Efficient memory reclaiming for mitigating sluggish response in mobile devices. ICCE-Berlin Minho Ju, Hyeonggyu Kim, Mincheol Kang, Soontae Kim
2015	J	`jnl`	Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho. IEEE Trans. Computers Tayyeb Mahmood, Seokin Hong, Soontae Kim
2015	J	`jnl`	Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories. IEEE Trans. Very Large Scale Integr. Syst. Jeongkyu Hong, Jesung Kim, Soontae Kim
2015	J	`jnl`	Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction. IEEE Trans. Computers Jongmin Lee, Soontae Kim
2015	J	`jnl`	Low-Cost Control Flow Protection via Available Redundancies in the Microprocessor Pipeline. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Abdur Rouf, Soontae Kim
2014	C	`conf`	Ternary cache: Three-valued MLC STT-RAM caches. ICCD Seokin Hong, Jongmin Lee, Soontae Kim
2013	A	`conf`	AVICA: an access-time variation insensitive L1 cache architecture. DATE Seokin Hong, Soontae Kim
2013	J	`jnl`	Fault buffers - Enabling near-true voltage scaling in variation-sensitive L1 caches. Des. Autom. Embed. Syst. Tayyeb Mahmood, Soontae Kim
2013	A*	`conf`	Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling. HPCA Tayyeb Mahmood, Soontae Kim, Seokin Hong
2013	C	`conf`	Performance-controllable shared cache architecture for multi-core soft real-time systems. ICCD Myoungjun Lee, Soontae Kim
2013	A*	`conf`	Skinflint DRAM system: Minimizing DRAM chip writes for low power. HPCA Yebin Lee, Soontae Kim, Seokin Hong, Jongmin Lee
2012	A	`conf`	Adopting TLB index-based tagging to data caches for tag energy reduction. ISLPED Jongmin Lee, Soontae Kim
2012	A	`conf`	DRAM power-aware rank scheduling. ISLPED Sukki Kim, Soontae Kim, Yebin Lee
2012	C	`conf`	ECC string: Flexible ECC management for low-cost error protection of L2 caches. ICCD Jeongkyu Hong, Soontae Kim
2012	—	`conf`	Low-cost control flow error protection by exploiting available redundancies in the pipeline. ASP-DAC Mohammad Abdur Rouf, Soontae Kim
2012	J	`jnl`	Predictive routing for mobile sinks in wireless sensor networks: a milestone-based approach. J. Supercomput. Kwangcheol Shin, Soontae Kim
2012	J	`jnl`	Resuscitating privacy-preserving mobile payment with customer in complete control. Pers. Ubiquitous Comput. Divyan Munirathnam Konidala, Made Harta Dwijaksara, Kwangjo Kim, Dongman Lee, Byoungcheon Lee, Daeyoung Kim, Soontae Kim
2012	J	`jnl`	Traffic management strategy for delay-tolerant networks. J. Netw. Comput. Appl. Kwangcheol Shin, Kyungjun Kim, Soontae Kim
2011	C	`conf`	ADSR: Angle-Based Multi-hop Routing Strategy for Mobile Wireless Sensor Networks. APSCC Kwangcheol Shin, Kyungjun Kim, Soontae Kim
2011	—	`conf`	DRAM energy reduction by prefetching-based memory traffic clustering. ACM Great Lakes Symposium on VLSI Yebin Lee, Soontae Kim
2011	Misc	`conf`	Dynamic scheduling algorithm and its schedulability analysis for certifiable dual-criticality systems. EMSOFT Taeju Park, Soontae Kim
2011	J	`jnl`	Enhanced buffer management policy that utilises message properties for delay-tolerant networks. IET Commun. Kwangcheol Shin, Soontae Kim
2011	Misc	`conf`	Realizing near-true voltage scaling in variation-sensitive l1 caches via fault buffers. CASES Tayyeb Mahmood, Soontae Kim
2011	A*	`conf`	Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits. MICRO Soontae Kim, Jongmin Lee, Jesung Kim, Seokin Hong
2011	A	`conf`	TLB index-based tagging for cache energy reduction. ISLPED Jongmin Lee, Seokin Hong, Soontae Kim
2010	—	`conf`	Fine-Grained Fault Tolerance for Process Variation-Aware Caches. ISVLSI Tayyeb Mahmood, Soontae Kim
2010	C	`conf`	Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU. ICCD Seokin Hong, Soontae Kim
2010	B	`conf`	Modeling and Evaluation of Control Flow Vulnerability in the Embedded System. MASCOTS Mohammad Abdur Rouf, Soontae Kim
2010	A	`conf`	SimTag: Exploiting tag bits similarity to improve the reliability of the data caches. DATE Jesung Kim, Soontae Kim, Yebin Lee
2010	—	`conf`	Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system. ACM Great Lakes Symposium on VLSI Soontae Kim, Jongmin Lee
2009	J	`jnl`	A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. IEEE Trans. Very Large Scale Integr. Syst. Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim
2009	A	`conf`	An energy-delay efficient 2-level data cache architecture for embedded system. ISLPED Jongmin Lee, Soontae Kim
2009	J	`jnl`	Reducing Area Overhead for Error-Protecting Large L2/L3 Caches. IEEE Trans. Computers Soontae Kim
2009	—	`conf`	TEPS: Transient Error Protection Utilizing Sub-word Parallelism. ISVLSI Seokin Hong, Soontae Kim
2007	C	`conf`	Improving the reliability of on-chip L2 cache using redundancy. ICCD Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan
2007	C	`conf`	Reducing ALU and Register File Energy by Dynamic Zero Detection. IPCCC Soontae Kim
2007	J	`jnl`	Reducing non-deterministic loads in low-power caches via early cache set resolution. Microprocess. Microsystems Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin
2006	A	`conf`	Area-efficient error protection for caches. DATE Soontae Kim
2004	J	`jnl`	Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues. Wirel. Networks J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, Soontae Kim
2004	J	`jnl`	Instruction Scheduling for Low Power. J. VLSI Signal Process. Amisha Parikh, Soontae Kim, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2004	J	`jnl`	Optimizing Leakage Energy Consumption in Cache Bitlines. Des. Autom. Embed. Syst. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2004	A	`conf`	Scheduling Reusable Instructions for Power Reduction. DATE Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin
2003	A	`conf`	Masking the Energy Behavior of DES Encryption. DATE Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang
2003	A	`conf`	On load latency in low-power caches. ISLPED Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John
2003	J	`jnl`	Partitioned instruction cache architecture for energy efficiency. ACM Trans. Embed. Comput. Syst. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin
2001	—	`conf`	Energy Behavior of Java Applications from the Memory Perspective. Java Virtual Machine Research and Technology Symposium Narayanan Vijaykrishnan, Mahmut T. Kandemir, Soontae Kim, Samarjeet Singh Tomar, Anand Sivasubramaniam, Mary Jane Irwin
2001	A	`conf`	Power-aware partitioned cache architectures. ISLPED Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali