Song Guo - RankMe

14 papers A 1C 1Journal 7Unranked 5

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	A deeply-pipelined FPGA-based SpMV accelerator with a hardware-friendly storage scheme. IEICE Electron. Express Song Guo, Yong Dou, Yuanwu Lei, Guiming Wu
2015	—	`conf`	Accelerating Molecular Dynamics Simulations on Heterogeneous Architecture. NCCET Yueqing Wang, Yong Dou, Song Guo, Yuanwu Lei, Baofeng Li, Qiang Wang
2015	J	`jnl`	An efficient multi-standard QC-LDPC decoder based on the row-layered decoding algorithm. IEICE Electron. Express Song Guo, Yong Dou, Yuanwu Lei, Rongchun Li, Yu Li
2015	—	`conf`	Designing Parallel Sparse Matrix Transposition Algorithm Using ELLPACK-R for GPUs. NCCET Song Guo, Yong Dou, Yuanwu Lei, Qiang Wang, Fei Xia, Jianning Chen
2015	J	`jnl`	面向定制结构的稀疏矩阵分块方法 (Sparse Matrix Blocking Method for Custom Architecture). 计算机科学 Guiming Wu, Miao Wang, Xianghui Xie, Yong Dou, Song Guo
2014	—	`conf`	A high throughput K-best detector on FPGA. BlackSeaCom Zhiqiang Liu, Jingfei Jiang, Yong Dou, Rongchun Li, Song Guo
2014	J	`jnl`	CPU-GPU hybrid parallel strategy for cosmological simulations. Concurr. Comput. Pract. Exp. Yueqing Wang, Yong Dou, Song Guo, Yuanwu Lei, Dan Zou
2014	J	`jnl`	Supernodal sparse Cholesky factorization on graphics processing units. Concurr. Comput. Pract. Exp. Dan Zou, Yong Dou, Song Guo, Rongchun Li, Lin Deng
2013	—	`conf`	A multi-standard efficient column-layered LDPC decoder for Software Defined Radio on GPUs. SPAWC Rongchun Li, Jie Zhou, Yong Dou, Song Guo, Dan Zou, Shi Wang
2013	J	`jnl`	High performance sparse matrix-vector multiplication on FPGA. IEICE Electron. Express Dan Zou, Yong Dou, Song Guo, Shi-Ce Ni
2012	J	`jnl`	Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA. IEICE Trans. Commun. Rongchun Li, Yong Dou, Yuanwu Lei, Shi-Ce Ni, Song Guo
2011	—	`conf`	FPGA Implementation of Variable-Precision Floating-Point Arithmetic. APPT Yuanwu Lei, Yong Dou, Song Guo, Jie Zhou
2011	C	`conf`	Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA. ICCD Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo
2010	A	`conf`	FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing. ICS Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen