Song Chen

182 papers A* 4A 5C 11Journal 92Unranked 70
YearRankTypeTitle / Venue / Authors
2026 J jnl
GoSteiner: Constructing Rectilinear Steiner Minimum Tree on Directed Graph.
ACM Trans. Design Autom. Electr. Syst.
Rong Sun, Qi Xu, Song Chen, Yi Kang, Bei Yu
2026 J jnl
Real-Time Compensation Framework for Large-Scale ReRAM-Based Sparse LU Factorization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weiran Chen, Zaitian Chen, Bei Yu, Song Chen, Yi Kang, Qi Xu
2026 J jnl
Throughput Maximization for Transformer Inference on Processing Near-Memory Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mengke Ge, Yingjian Zhong, Song Chen, Yi Kang
2025 J jnl
A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure.
IEEE Trans. Very Large Scale Integr. Syst.
Song Wang, Yixin Guo, Wei Tao, Xuerong Jia, Fujun Bai, Jie Tan, Yubing Wang, Liang Bai, Fuzhi Guo, Qi Liu, Jin Li, Peng Yin, Fenning Liu, Jing Liu, Xiaodong Long, Yanwu Han, Zhongcheng Yu, Mengzi Cheng, Song Chen, Xiping Jiang
2025 J jnl
A neuromorphic hardware architecture based on TTFS coding with temporal quantization for spiking neural networks.
Integr.
Yuxuan Yang, Qihu Xie, Zihao Xuan, Song Chen, Yi Kang
2025 — conf
AIPlace: Analog IC Placement with Multi-Task Learning Framework.
ASP-DAC
Lijie Wang, Jing Wang, Song Chen, Qi Xu
2025 J jnl
Allspark: Workload Orchestration for Visual Transformers on Processing In-Memory Systems.
IEEE Trans. Computers
Mengke Ge, Junpeng Wang, Binhan Chen, Yingjian Zhong, Haitao Du, Song Chen, Yi Kang
2025 J jnl
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling.
IEEE Trans. Very Large Scale Integr. Syst.
Haitao Du, Hairui Zhu, Song Chen, Yi Kang
2025 J jnl
Comma: A Communication-Minimized Model-Architecture Framework for Efficient Convolution Acceleration.
IEEE Trans. Very Large Scale Integr. Syst.
Wendi Sun, Yifan Wang, Xu Cao, Yao Ge, Song Chen, Yi Kang
2025 J jnl
DIVIDE: Efficient RowHammer Defense via In-DRAM Cache-Based Hot Data Isolation.
IEEE Trans. Computers
Haitao Du, Yuxuan Yang, Song Chen, Yi Kang
2025 J jnl
EI²Det: Edge-Guided Illumination-Aware Interactive Learning for Visible-Infrared Object Detection.
IEEE Trans. Circuits Syst. Video Technol.
Ke Hu, Yudong He, Yuan Li, Jiayu Zhao, Song Chen, Yi Kang
2025 J jnl
Fast shallow multi-subnet detector for real-time object detection.
Eng. Appl. Artif. Intell.
Yuan Li, Mengdie Song, Ke Hu, Song Chen, Yi Kang
2025 J jnl
HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N:M Sparsity.
ACM Trans. Design Autom. Electr. Syst.
Yuang Ma, Yulong Meng, Zihao Xuan, Song Chen, Yi Kang
2025 J jnl
IOPS: A Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product.
IEEE Trans. Computers
Wenhao Sun, Wendi Sun, Song Chen, Yi Kang
2025 — conf
Machine Learning-Based Real-Time Detection of Power Analysis Attacks Using Supply Voltage Comparisons.
ASP-DAC
Nan Wang, Ruichao Liu, Yufeng Shan, Yu Zhu, Song Chen
2025 J jnl
PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu
2025 — conf
ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast Simulator.
ASP-DAC
Xinfei Liu, Siting Liu, Bei Yu, Song Chen, Qi Xu
2025 A* conf
YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AI.
DAC
Zihao Xuan, Yuxuan Yang, Wei Xuan, Zijia Su, Song Chen, Yi Kang
2024 J jnl
AD
ACM Trans. Design Autom. Electr. Syst.
Yongtian Bi, Qi Xu, Hao Geng, Song Chen, Yi Kang
2024 J jnl
Allspark: Workload Orchestration for Visual Transformers on Processing In-Memory Systems.
CoRR
Mengke Ge, Junpeng Wang, Binhan Chen, Yingjian Zhong, Haitao Du, Song Chen, Yi Kang
2024 J jnl
Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity.
IEEE Trans. Computers
Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen, Yi Kang
2024 — conf
Communication Minimized Model-Architecture Co-design for Efficient Convolution Acceleration.
ACM Great Lakes Symposium on VLSI
Wendi Sun, Wenhao Sun, Yifan Wang, Yi Kang, Song Chen
2024 A* conf
DALDet: Depth-Aware Learning Based Object Detection for Autonomous Driving.
AAAI
Ke Hu, Tongbo Cao, Yuan Li, Song Chen, Yi Kang
2024 C conf
DP-FFN: Block-Based Dynamic Pooling for Accelerating Feed-Forward Layers in Transformers.
ISCAS
Jie Tang, Shuai Wang, Song Chen, Yi Kang
2024 — conf
Efficient Object Detection via Fine-Grained Regularization with Global Initialization.
ICPR (3)
Binhan Chen, Qiaojun Wu, Song Chen, Yi Kang
2024 J jnl
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration.
ACM Trans. Archit. Code Optim.
Haitao Du, Yuhan Qin, Song Chen, Yi Kang
2024 J jnl
Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay.
ACM Trans. Design Autom. Electr. Syst.
Bo Yang, Qi Xu, Hao Geng, Song Chen, Bei Yu, Yi Kang
2024 J jnl
Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Qi Xu, Lijie Wang, Jing Wang, Lin Cheng, Song Chen, Yi Kang
2024 — conf
ILP-based Multi-Branch CNNs Mapping on Processing-in-Memory Architecture.
AICAS
Haodong Han, Junpeng Wang, Bo Ding, Song Chen
2024 J jnl
Load Balanced PIM-Based Graph Processing.
ACM Trans. Design Autom. Electr. Syst.
Xiang Zhao, Song Chen, Yi Kang
2024 A conf
Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner.
DATE
Bo Yang, Qi Xu, Hao Geng, Song Chen, Yi Kang
2024 J jnl
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen, Yi Kang
2024 A conf
Parallel Multi-Objective Bayesian Optimization Framework for CGRA Microarchitecture.
DATE
Bing Li, Wendi Sun, Xiaobing Ni, Kaixuan He, Qi Xu, Song Chen, Yi Kang
2024 — conf
SPVT: Spiked Pyramid Vision Transformer.
AICAS
Yazhuo Guo, Yuhan Qin, Song Chen, Yi Kang
2024 J jnl
SparseMap: Loop Mapping for Sparse CNNs on Streaming Coarse-grained Reconfigurable Array.
CoRR
Xiaobing Ni, Mengke Ge, Jiaheng Ruan, Song Chen, Yi Kang
2023 — conf
A Lightweight Stereo Matching Neural Network Based on Depthwise Separable Convolution.
ICTA
Zetao Guo, Junpeng Wang, Song Chen, Yi Kang
2023 J jnl
AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multi-Bit Compute and Interconnect.
CoRR
Zihao Xuan, Song Chen, Yi Kang
2023 — conf
An 1.38nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory.
BioCAS
Wenbing Fang, Zihao Xuan, Song Chen, Yi Kang
2023 J jnl
BandMap: Application Mapping with Bandwidth Allocation forCoarse-Grained Reconfigurable Array.
CoRR
Xiaobing Ni, Jiaheng Ruan, Mengke Ge, Wendi Sun, Song Chen, Yi Kang
2023 J jnl
Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity.
CoRR
Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen, Yi Kang
2023 J jnl
BusMap: Application Mapping With Bus Routing for Coarse-Grained Reconfigurable Array.
IEEE Trans. Circuits Syst. II Express Briefs
Xiaobing Ni, Mengke Ge, Yongjin Tao, Wendi Sun, Feixiang Duan, Xuefei Bai, Qi Xu, Song Chen, Yi Kang
2023 J jnl
DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems.
ACM Trans. Design Autom. Electr. Syst.
Junpeng Wang, Haitao Du, Bo Ding, Qi Xu, Song Chen, Yi Kang
2023 — conf
Efficient Transistor-Level QDI Asynchronous Switch for Neuromorphic Systems.
NEWCAS
Shahzad Haider, Junhao Liang, Song Chen
2023 — conf
Fine-Grained Transistor-Level QDI Asynchronous Crossbar Switch.
SOCC
Shahzad Haider, Ke Hu, Song Chen
2023 — conf
GGPA: A General Graph Processing Architecture with Flexible Execution Paradigm.
CF
Bin Zhang, Haitao Du, Song Chen, Yi Kang
2023 — conf
Granular Transistor-Level Approaches for QDI Asynchronous Crossbar Switches.
MWSCAS
Shahzad Haider, Song Chen
2023 J jnl
Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits.
CoRR
Qi Xu, Lijie Wang, Jing Wang, Song Chen, Lin Cheng, Yi Kang
2023 J jnl
IOPS: An Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product.
CoRR
Wenhao Sun, Wendi Sun, Song Chen, Yi Kang
2023 J jnl
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.
ACM Trans. Design Autom. Electr. Syst.
Bo Ding, Jinglei Huang, Qi Xu, Junpeng Wang, Song Chen, Yi Kang
2023 J jnl
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM.
CoRR
Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen, Yi Kang
2023 J jnl
Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems.
IEEE Trans Autom. Sci. Eng.
Qi Xu, Junpeng Wang, Bo Yuan, Qi Sun, Song Chen, Bei Yu, Yi Kang, Feng Wu
2023 J jnl
Resist: Robust Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems.
IEEE Trans. Circuits Syst. II Express Briefs
Yongtian Bi, Qi Xu, Hao Geng, Song Chen, Yi Kang
2023 A* conf
Restructure-Tolerant Timing Prediction via Multimodal Fusion.
DAC
Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu
2023 J jnl
Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays.
IEEE Trans. Very Large Scale Integr. Syst.
Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Song Chen, Yi Kang
2023 J jnl
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources.
ACM Trans. Design Autom. Electr. Syst.
Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang
2022 J jnl
A Resource-Efficient Pipelined Architecture for Real-Time Semi-Global Stereo Matching.
IEEE Trans. Circuits Syst. Video Technol.
Zhimin Lu, Jue Wang, Zhiwei Li, Song Chen, Feng Wu
2022 J jnl
Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qi Xu, Wenhao Sun, Song Chen, Yi Kang, Xiaoqing Wen
2022 — conf
DRGS: Low-Precision Full Quantization of Deep Neural Network with Dynamic Rounding and Gradient Scaling for Object Detection.
DMBD (1)
Qiaojun Wu, Yuan Li, Song Chen, Yi Kang
2022 J jnl
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qi Xu, Hao Geng, Tianming Ni, Song Chen, Bei Yu, Yi Kang, Xiaoqing Wen
2022 J jnl
Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICs.
IEEE Trans. Circuits Syst. II Express Briefs
Mengke Ge, Xiaobing Ni, Song Chen, Yi Kang
2022 J jnl
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qi Xu, Hao Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, Xiaoqing Wen
2022 — conf
Multi-scale Lightweight Neural Network for Real-Time Object Detection.
PRICAI (3)
Yuan Li, Qiaojun Wu, Song Chen, Yi Kang
2022 C conf
PCFBCD: An Innovative Approach to Accelerating Collaborative Filtering.
ISCAS
Bin Zhang, Haitao Du, Song Chen, Yi Kang
2022 C conf
Real-time CNN-based keypoint detector with Sobel filter and descriptor trained with keypoint candidates.
ICMV
Ke Hu, Xun Yuan, Song Chen
2022 J jnl
Real-time infrared small target detection network and accelerator design.
Integr.
Ke Hu, Wenhao Sun, Zhongbo Nie, Ran Cheng, Song Chen, Yi Kang
2022 — conf
SAUST: A Scheme for Acceleration of Unstructured Sparse Transformer.
ICTA
Yifan Song, Shunpeng Zhao, Song Chen, Yi Kang
2022 J jnl
Sense: Model Hardware Co-design for Accelerating Sparse Neural Networks.
CoRR
Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Junpeng Wang, Yi Kang, Song Chen
2022 J jnl
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips.
ACM Trans. Design Autom. Electr. Syst.
Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen, Jinglei Huang, Yi Kang, Feng Wu
2022 J jnl
Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs.
CoRR
Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang
2021 — conf
A Low Power Branch Prediction for Deep Learning on RISC-V Processor.
ASAP
Mingjian Sun, Yuan Li, Song Chen, Yi Kang
2021 — conf
A Low-latency NoC Router Priority Scheme for BFS algorithm.
ICTA
Lei Ding, Haitao Du, Song Chen, Yi Kang
2021 — conf
A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier.
NVMSA
Qiqiao Wu, Wenhao Sun, Junpeng Wang, Xuefei Bai, Feng Zhang, Song Chen, Yi Kang
2021 — conf
Effects of using Multi Voltage Threshold Transistors in Asynchronous Circuits.
ASICON
Shahzad Haider, Song Chen
2021 A conf
Reliability-Driven Neuromorphic Computing Systems Design.
DATE
Qi Xu, Junpeng Wang, Hao Geng, Song Chen, Xiaoqing Wen
2021 J jnl
Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips.
CoRR
Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen, Jinglei Huang, Yi Kang, Feng Wu
2020 J jnl
Fault tolerance in memristive crossbar-based neuromorphic computing systems.
Integr.
Qi Xu, Song Chen, Hao Geng, Bo Yuan, Bei Yu, Feng Wu, Zhengfeng Huang
2020 — conf
Fault-Tolerant-Driven Clustering for Large Scale Neuromorphic Computing Systems.
AICAS
Yuting Wu, Bo Ding, Qi Xu, Song Chen
2020 J jnl
Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Song Chen, Mengke Ge, Zhigang Li, Jinglei Huang, Qi Xu, Feng Wu
2020 J jnl
Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Song Chen, Jinglei Huang, Xiaodong Xu, Bo Ding, Qi Xu
2020 J jnl
Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC.
ACM Trans. Design Autom. Electr. Syst.
Qi Xu, Hao Geng, Song Chen, Bei Yu, Feng Wu
2020 J jnl
Realtime CNN-based Keypoint Detector with Sobel Filter and CNN-based Descriptor Trained with Keypoint Candidates.
CoRR
Xun Yuan, Ke Hu, Song Chen
2020 C conf
Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems.
ISCAS
Junpeng Wang, Qi Xu, Bo Yuan, Song Chen, Bei Yu, Feng Wu
2020 A conf
SaD-SLAM: A Visual SLAM Based on Semantic and Depth Information.
IROS
Xun Yuan, Song Chen
2020 — conf
Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems.
ACM Great Lakes Symposium on VLSI
Mengke Ge, Qi Xu, Huajie Ruan, Xiaobing Ni, Song Chen, Yi Kang
2019 J jnl
Adaptive 3D-IC TSV Fault Tolerance Structure Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Song Chen, Qi Xu, Bei Yu
2019 — conf
An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network.
ASICON
Baicheng Liu, Song Chen, Yi Kang, Feng Wu
2019 — conf
Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN.
ASICON
Tianzhi Xue, Baicheng Liu, Wenhao Sun, Song Chen, Yi Kang, Feng Wu
2019 J jnl
Generalized Fault-Tolerance Topology Generation for Application Specific Network-on-Chips.
CoRR
Song Chen, Mengke Ge, Zhigang Li, Jinglei Huang, Qi Xu, Feng Wu
2019 J jnl
High throughput hardware architecture for accurate semi-global matching.
Integr.
Yan Li, Zhiwei Li, Chen Yang, Wei Zhong, Song Chen
2019 J jnl
Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis.
Integr.
Nan Wang, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu
2019 C conf
Low-Resource Hardware Architecture for Semi-Global Stereo Matching.
ISCAS
Jue Wang, Zhiwei Li, Lan Yao, Song Chen, Feng Wu
2019 J jnl
Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems.
Integr.
Jinglei Huang, Xiaodong Xu, Nan Wang, Song Chen
2018 J jnl
Adaptive 3D-IC TSV Fault Tolerance Structure Generation.
CoRR
Song Chen, Qi Xu, Bei Yu
2018 J jnl
Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems.
CoRR
Song Chen, Jinglei Huang, Xiaodong Xu, Qi Xu
2018 J jnl
Lagrangian relaxation-based routing path allocation for application-specific network-on-chips.
Integr.
Jinglei Huang, Wei Zhong, Zhigang Li, Song Chen
2018 — conf
Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC.
ACM Great Lakes Symposium on VLSI
Qi Xu, Song Chen, Bei Yu, Feng Wu
2018 J jnl
Power-gating-aware scheduling with effective hardware resources optimization.
Integr.
Nan Wang, Wei Zhong, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu
2018 J jnl
Security-Aware Task Scheduling Using Untrusted Components in High-Level Synthesis.
IEEE Access
Nan Wang, Song Chen, Jianmo Ni, Xiaofeng Ling, Yu Zhu
2018 — conf
Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints.
ISVLSI
Nan Wang, Manting Yao, Dongxu Jiang, Song Chen, Yu Zhu
2017 — conf
A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth.
ASICON
Zhiwei Li, Yan Li, Song Chen, Feng Wu
2017 — conf
An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs.
ACM Great Lakes Symposium on VLSI
Xiaodong Xu, Qi Xu, Jinglei Huang, Song Chen
2017 J jnl
AutoNFT: Architecture synthesis for hardware DFT of length-of-coprime-number products.
Integr.
Gan Feng, Lan Yao, Song Chen
2017 J jnl
Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qi Xu, Song Chen, Xiaodong Xu, Bei Yu
2017 J jnl
Fast thermal analysis for fixed-outline 3D floorplanning.
Integr.
Qi Xu, Song Chen
2017 — conf
High throughput hardware architecture for accurate semi-global matching.
ASP-DAC
Yan Li, Chen Yang, Wei Zhong, Zhiwei Li, Song Chen
2017 — conf
Integer linear programming based fault-tolerant topology synthesis for application-specific NoC.
ASICON
Zhigang Li, Jinglei Huang, Qi Xu, Song Chen
2017 — conf
Memristor-based material implication logic design for full adders.
ASICON
Mengting Li, Wenhao Sun, Zhimin Lu, Song Chen, Feng Wu
2017 — conf
Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs.
SLIP
Jinglei Huang, Xiaodong Xu, Lan Yao, Song Chen
2016 J jnl
Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning.
Appl. Soft Comput.
Qi Xu, Song Chen, Bin Li
2016 J jnl
Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect.
ACM Trans. Design Autom. Electr. Syst.
Jinglei Huang, Song Chen, Wei Zhong, Wenchao Zhang, Shengxi Diao, Fujiang Lin
2016 J jnl
Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design.
IEEE Trans. Very Large Scale Integr. Syst.
Nan Wang, Wei Zhong, Cong Hao, Song Chen, Takeshi Yoshimura, Yu Zhu
2016 — conf
Real-Time Hardware Stereo Matching Using Guided Image Filter.
ACM Great Lakes Symposium on VLSI
Chen Yang, Yan Li, Wei Zhong, Song Chen
2015 — conf
A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi.
ASICON
Wenchao Zhang, Song Chen, Xuefei Bai, Dajiang Zhou
2015 — conf
Irregularly shaped voltage islands generation with hazard and heal strategy.
ISQED
Zhen Meng, Song Chen, Lu Huang
2015 — conf
Lagrangian relaxation based topology synthesis for Application-Specific Network-on-Chips.
ASICON
Jinglei Huang, Zhigang Li, Wei Zhong, Song Chen
2014 J jnl
Floorplanning and Topology Generation for Application-Specific Network-on-Chip.
CoRR
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2014 J jnl
Leakage Power Aware Scheduling in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nan Wang, Song Chen, Cong Hao, Haoran Zhang, Takeshi Yoshimura
2014 J jnl
Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nan Wang, Song Chen, Wei Zhong, Nan Liu, Takeshi Yoshimura
2014 J jnl
Network flow-based simultaneous retiming and slack budgeting for low power design.
CoRR
Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
2014 J jnl
Voltage and Level-Shifter Assignment Driven Floorplanning.
CoRR
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2013 — conf
Delay-driven layer assignment in global routing under multi-tier interconnect structure.
ISPD
Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto
2013 J jnl
Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Wei Zhong, Song Chen, Bo Huang, Takeshi Yoshimura, Satoshi Goto
2013 — conf
Interconnection allocation between functional units and registers in High-Level Synthesis.
ASICON
Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura, Min-You Wu
2013 — conf
Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs.
ASICON
Wei Zhong, Song Chen, Yang Geng, Takeshi Yoshimura
2013 — conf
Min-cut based leakage power aware scheduling in high-level synthesis.
ISQED
Nan Wang, Song Chen, Takeshi Yoshimura
2013 C conf
Mobility overlap-removal based leakage power aware scheduling in high-level synthesis.
ISCAS
Nan Wang, Song Chen, Yuhuan Sun, Takeshi Yoshimura
2013 — conf
Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis.
ASP-DAC
Cong Hao, Song Chen, Takeshi Yoshimura
2013 — conf
Power and resource aware scheduling with multiple voltages.
ASICON
Haoran Zhang, Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura
2013 J jnl
Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs.
IEICE Trans. Electron.
Nan Liu, Song Chen, Takeshi Yoshimura
2013 C conf
Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis.
ISCAS
Bo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura
2012 — conf
Application-Specific Network-on-Chip synthesis with topology-aware floorplanning.
SBCCI
Bo Huang, Song Chen, Wei Zhong, Takeshi Yoshimura
2012 J jnl
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips.
IEICE Trans. Electron.
Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto
2012 J jnl
Floorplanning for High Utilization of Heterogeneous FPGAs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Nan Liu, Song Chen, Takeshi Yoshimura
2012 — conf
Linear optimal one-sided single-detour algorithm for untangling twisted bus.
ASP-DAC
Tao Lin, Sheqin Dong, Song Chen, Satoshi Goto
2012 J jnl
Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Haiqi Wang, Sheqin Dong, Tao Lin, Song Chen, Satoshi Goto
2012 — conf
Port assignment for interconnect reduction in high-level synthesis.
VLSI-DAT
Cong Hao, Song Chen, Takeshi Yoshimura
2012 A conf
Practically scalable floorplanning with voltage island generation.
ISLPED
Song Chen, Xiaolin Zhang, Takeshi Yoshimura
2011 — conf
An effecient level-shifter floorplanning method for Multi-voltage design.
ASICON
Xiaolin Zhang, Zhi Lin, Song Chen, Takeshi Yoshimura
2011 — conf
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion.
ISQED
Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto
2011 C conf
Floorplanning driven Network-on-Chip synthesis for 3-D SoCs.
ISCAS
Wei Zhong, Song Chen, Fei Ma, Takeshi Yoshimura, Satoshi Goto
2011 — conf
Floorplanning for high utilization of heterogeneous FPGAs.
ISQED
Nan Liu, Song Chen, Takeshi Yoshimura
2011 — conf
Mobility overlap-removal based timing-constrained scheduling.
ASICON
Song Chen, Yuan Yao, Takeshi Yoshimura
2011 — conf
Network flow-based simultaneous retiming and slack budgeting for low power design.
ASP-DAC
Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto
2011 — conf
Novel and efficient min cut based voltage assignment in gate level.
ISQED
Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto
2011 — conf
Through-Silicon-Via assignment for 3D ICs.
ASICON
Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto
2010 — conf
A revisit to voltage partitioning problem.
ACM Great Lakes Symposium on VLSI
Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto
2010 — conf
Floorplanning and topology generation for application-specific network-on-chip.
ASP-DAC
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2010 J jnl
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints.
Integr.
Song Chen, Takeshi Yoshimura
2010 — conf
Post-scheduling frequency assignment for energy-efficient high-level synthesis.
APCCAS
Ru Liu, Song Chen, Takeshi Yoshimura
2010 J jnl
Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Song Chen, Jianwei Shen, Wei Guo, Mei-Fang Chiang, Takeshi Yoshimura
2010 C conf
Whitespace insertion for through-silicon via planning on 3-D SoCs.
ISCAS
Wei Zhong, Song Chen, Takeshi Yoshimura
2009 — conf
A generalized V-shaped multilevel method for large scale floorplanning.
ISQED
Song Chen, Zheng Xu, Takeshi Yoshimura
2009 J jnl
Exploration of Schedule Space by Random Walk.
Inf. Media Technol.
Liangwei Ge, Song Chen, Takeshi Yoshimura
2009 J jnl
Exploration of Schedule Space by Random Walk.
IPSJ Trans. Syst. LSI Des. Methodol.
Liangwei Ge, Song Chen, Takeshi Yoshimura
2009 J jnl
Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Song Chen, Liangwei Ge, Mei-Fang Chiang, Takeshi Yoshimura
2009 J jnl
Voltage and Level-Shifter Assignment Driven Floorplanning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto
2009 — conf
Voltage-island driven floorplanning considering level-shifter positions.
ACM Great Lakes Symposium on VLSI
Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen
2008 J jnl
A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition.
Inf. Media Technol.
Liangwei Ge, Song Chen, Yuichi Nakamura, Takeshi Yoshimura
2008 J jnl
A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition.
IPSJ Trans. Syst. LSI Des. Methodol.
Liangwei Ge, Song Chen, Yuichi Nakamura, Takeshi Yoshimura
2008 J jnl
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Song Chen, Takeshi Yoshimura
2007 — conf
A stable fixed-outline floorplanning method.
ISPD
Song Chen, Takeshi Yoshimura
2007 J jnl
Max-Flow Scheduling in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Liangwei Ge, Song Chen, Kazutoshi Wakabayashi, Takashi Takenaka, Takeshi Yoshimura
2006 C conf
Buffer planning based on block exchanging.
ISCAS
Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
2006 — conf
On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence.
APCCAS
Song Chen, Takeshi Yoshimura
2006 J jnl
VLSI Block Placement With Alignment Constraints.
IEEE Trans. Circuits Syst. II Express Briefs
Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng
2005 C conf
A New Buffer Planning Algorithm Based on Room Resizing.
EUC
Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen
2005 — conf
Buffer Planning Algorithm Based on Partial Clustered Floorplanning.
ISQED
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005 J jnl
Buffer planning as an Integral part of floorplanning with consideration of routing congestion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu
2005 — conf
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.
ISQED
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2005 — conf
Performance constrained floorplanning based on partial clustering [IC layout].
ISCAS (2)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng
2005 — conf
VLSI block placement with alignment constraints based on corner block list.
ISCAS (6)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng
2004 J jnl
A buffer planning algorithm for chip-level floorplanning.
Sci. China Ser. F Inf. Sci.
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 — conf
A buffer planning algorithm with congestion optimization.
ASP-DAC
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 — conf
Buffer allocation algorithm with consideration of routing congestion.
ASP-DAC
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2004 J jnl
Fast Evaluation of Bounded Slice-Line Grid.
J. Comput. Sci. Technol.
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu
2003 — conf
A buffer planning algorithm based on dead space redistribution.
ASP-DAC
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
An integrated floorplanning with an efficient buffer planning algorithm.
ISPD
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
Arbitrary convex and concave rectilinear block packing based on corner block list.
ISCAS (5)
Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu
2003 A* conf
Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
DAC
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 — conf
Evaluating a bounded slice-line grid assignment in O(nlogn) time.
ISCAS (4)
Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu
2003 J jnl
VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Sheqin Dong, Xianlong Hong, Song Chen, Xin Qi, Ruijie Wang, Jun Gu
2003 — conf
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing.
ASP-DAC
Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu