Somnath Paul

73 papers A* 3A 9B 1C 4Misc 5Journal 33Unranked 18
YearRankTypeTitle / Venue / Authors
2025 J jnl
A hybrid fuzzy decision-making framework for methodological analysis of barriers to low-carbon technology adoption in net-zero manufacturing supply chains.
Eng. Appl. Artif. Intell.
Puspendu Giri, Bijoy Krishna Debnath, Somnath Paul
2025 J jnl
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.
Commun. ACM
Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Mohammad Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2025 J jnl
On adjacency and (signless) Laplacian spectra of centralizer and co-centralizer graphs of some finite non-abelian groups.
Electron. J. Graph Theory Appl.
Jharna Kalita, Somnath Paul
2023 A* conf
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis.
ISCA
Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2021 B conf
GenomicsBench: A Benchmark Suite for Genomics.
ISPASS
Arun Subramaniyan, Yufeng Gu, Timothy Dunn, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das
2021 J jnl
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities.
IEEE Trans. Very Large Scale Integr. Syst.
Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim
2020 — conf
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads.
VLSI Circuits
Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah, Vivek De
2020 — conf
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit.
VLSI Circuits
Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De
2020 J jnl
On the sum of the distance signless Laplacian eigenvalues of a graph and some inequalities involving them.
Discret. Math. Algorithms Appl.
Abdollah Alhevaz, Maryam Baghipur, Ebrahim Hashemi, Somnath Paul
2019 J jnl
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits
Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018 — conf
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
ISSCC
Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep P. Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De
2018 J jnl
Conjugate Laplacian matrices of a graph.
Discret. Math. Algorithms Appl.
Somnath Paul
2018 J jnl
On the distance signless Laplacian spectral radius and the distance signless Laplacian energy of graphs.
Discret. Math. Algorithms Appl.
Abdollah Alhevaz, Maryam Baghipur, Somnath Paul
2018 — conf
Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting.
BioCAS
Bruno U. Pedroni, Sadique Sheik, Hesham Mostafa, Somnath Paul, Charles Augustine, Gert Cauwenberghs
2018 J jnl
The spectra of a new join of graphs.
Discret. Math. Algorithms Appl.
Somnath Paul
2017 J jnl
A Sub-cm
IEEE J. Solid State Circuits
Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Tao Wang, Sriram R. Vangal, James W. Tschanz, Vivek De
2017 J jnl
Adaptive ECC for Tailored Protection of Nanoscale Memory.
IEEE Des. Test
Dongyeob Shin, Jongsun Park, Jangwon Park, Somnath Paul, Swarup Bhunia
2017 J jnl
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware.
IEEE Trans. Very Large Scale Integr. Syst.
Wenchao Qian, Christopher Babecki, Robert Karam, Somnath Paul, Swarup Bhunia
2017 C conf
Event-driven random backpropagation: Enabling neuromorphic deep learning machines.
ISCAS
Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis
2017 J jnl
Membrane-Dependent Neuromorphic Learning Rule for Unsupervised Spike Pattern Detection.
CoRR
Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs
2017 J jnl
Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications.
ACM J. Emerg. Technol. Comput. Syst.
Robert Karam, Somnath Paul, Ruchir Puri, Swarup Bhunia
2017 J jnl
Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning.
CoRR
Georgios Detorakis, Sadique Sheik, Charles Augustine, Somnath Paul, Bruno U. Pedroni, Nikil D. Dutt, Jeffrey L. Krichmar, Gert Cauwenberghs, Emre Neftci
2016 J jnl
An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications.
IEEE Trans. Computers
Christopher Babecki, Wenchao Qian, Somnath Paul, Robert Karam, Swarup Bhunia
2016 — conf
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS.
VLSI Circuits
Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James W. Tschanz, Vivek De
2016 J jnl
Event-driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines.
CoRR
Emre Neftci, Charles Augustine, Somnath Paul, Georgios Detorakis
2016 J jnl
Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity.
CoRR
Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
2016 — conf
Forward table-based presynaptic event-triggered spike-timing-dependent plasticity.
BioCAS
Bruno U. Pedroni, Sadique Sheik, Siddharth Joshi, Georgios Detorakis, Somnath Paul, Charles Augustine, Emre Neftci, Gert Cauwenberghs
2016 — conf
Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection.
BioCAS
Sadique Sheik, Somnath Paul, Charles Augustine, Gert Cauwenberghs
2016 J jnl
On distance and distance Laplacian spectra of corona of two graphs.
Discret. Math. Algorithms Appl.
Somnath Paul
2016 C conf
Synaptic sampling in hardware spiking neural networks.
ISCAS
Sadique Sheik, Somnath Paul, Charles Augustine, Chinnikrishna Kothapalli, Muhammad M. Khellah, Gert Cauwenberghs, Emre Neftci
2015 J jnl
Exploring Spin Transfer Torque Devices for Unconventional Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Kaushik Roy, Deliang Fan, Xuanyao Fong, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, Saibal Mukhopadhyay
2015 J jnl
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Somnath Paul, Aswin Raghav Krishna, Wenchao Qian, Robert Karam, Swarup Bhunia
2014 J jnl
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
2014 J jnl
A note on the Distance spectral radius of some graphs.
Discret. Math. Algorithms Appl.
Milan Nath, Somnath Paul
2014 A conf
Energy-efficient hardware acceleration through computing in the memory.
DATE
Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri
2014 J jnl
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks.
IEEE Trans. Very Large Scale Integr. Syst.
Anandaroop Ghosh, Somnath Paul, Jongsun Park, Swarup Bhunia
2014 J jnl
On the Minimal Distance spectral radius in the Class of bicyclic graphs.
Discret. Math. Algorithms Appl.
Milan Nath, Somnath Paul
2014 — conf
Robust low-power reconfigurable computing with a variation-aware preferential design approach.
ICICDT
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
2013 — conf
An Improved
VDAT
Somnath Paul, Abhijit Dana, Soumya Pandit
2013 J jnl
Graph Transformation and Distance spectral radius.
Discret. Math. Algorithms Appl.
Milan Nath, Somnath Paul
2013 J jnl
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis.
IEEE Trans. Computers
Seetharam Narasimhan, Dongdong Du, Rajat Subhra Chakraborty, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia
2013 — conf
Reconfigurable ECC for adaptive protection of memory.
MWSCAS
Abhishek Basak, Somnath Paul, Jangwon Park, Jongsun Park, Swarup Bhunia
2012 Misc conf
Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks.
VLSI Design
Anandaroop Ghosh, Somnath Paul, Swarup Bhunia
2012 J jnl
On the Maximal Distance spectral radius in a Class of bicyclic Graphs.
Discret. Math. Algorithms Appl.
Somnath Paul
2012 Misc conf
Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory.
VLSI Design
Lei Wang, Somnath Paul, Swarup Bhunia
2011 J jnl
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement.
IEEE Trans. Very Large Scale Integr. Syst.
Somnath Paul, Swarup Bhunia
2011 J jnl
Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
2011 A conf
Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only).
FPGA
Somnath Paul, Swarup Bhunia
2011 — conf
NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing.
NANOARCH
Xinmu Wang, Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
2011 J jnl
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache.
IEEE Trans. Computers
Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia
2010 J jnl
Low-overhead
ACM Trans. Design Autom. Electr. Syst.
Somnath Paul, Hamid Mahmoodi, Swarup Bhunia
2010 — conf
Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.
HOST
Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia
2010 — conf
System level self-healing for parametric yield and reliability improvement under power bound.
AHS
Seetharam Narasimhan, Somnath Paul, Rajat Subhra Chakraborty, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, Swarup Bhunia
2010 A conf
VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.
ISLPED
Somnath Paul, Swarup Bhunia
2009 A conf
A circuit-software co-design approach for improving EDP in reconfigurable frameworks.
ICCAD
Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia
2009 A conf
A variation-aware preferential design approach for memory based reconfigurable computing.
ICCAD
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
2009 — conf
Computing with nanoscale memory: Model and architecture.
NANOARCH
Somnath Paul, Swarup Bhunia
2009 J jnl
Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping.
IET Comput. Digit. Tech.
Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, Swarup Bhunia
2009 A conf
MERO: A Statistical Approach for Hardware Trojan Detection.
CHES
Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia
2008 Misc conf
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits.
VLSI Design
Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia
2008 A* conf
Collective computing based on swarm intelligence.
DAC
Seetharam Narasimhan, Somnath Paul, Swarup Bhunia
2008 A conf
Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement.
DATE
Yu Zhou, Somnath Paul, Swarup Bhunia
2008 A conf
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches.
ICCAD
Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia
2008 — conf
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices.
ASP-DAC
Somnath Paul, Swarup Bhunia
2008 — conf
On-Demand Transparency for Improving Hardware Trojan Detectability.
HOST
Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia
2008 A* conf
Reconfigurable computing using content addressable memory for improved performance and resource usage.
DAC
Somnath Paul, Swarup Bhunia
2008 — conf
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect.
ISQED
Yu Zhou, Somnath Paul, Swarup Bhunia
2007 — conf
Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration.
ISQED
Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia
2007 C conf
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.
IOLTS
Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
2007 A conf
Low-overhead design technique for calibration of maximum frequency at multiple operating points.
ICCAD
Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia
2007 C conf
Memory based computation using embedded cache for processor yield and reliability improvement.
ICCD
Somnath Paul, Swarup Bhunia
2007 Misc conf
VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips.
VTS
Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia
1998 Misc conf
Hardware/Software Co-design of a High-end Mixed Signal Microcontroller.
VLSI Design
Pradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta