Somayeh Timarchi

31 papers C 2Journal 25Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
Balancing precision and efficiency: an approximate multiplier with built-in error compensation for error-resilient applications.
J. Supercomput.
Ladan Sayadi, Abdolah Amirany, Mohammad Hossein Moaiyeri, Somayeh Timarchi
2025 J jnl
Load balanced sub-tree decomposition algorithm for solving Mixed Integer Linear Programming models in behavioral synthesis.
Comput. Electr. Eng.
Mahmood Fazlali, Mina Mirhosseini, Mahdi Movahedian Moghaddam, Somayeh Timarchi
2025 J jnl
Low-Power Resource-Efficient FPGA Implementation of Modified FitzHugh-Nagumo Neuron for Spiking Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Reza Badiei, Somayeh Timarchi, Alireza Zakaleh
2023 J jnl
High-Performance Memory Allocation on FPGA With Reduced Internal Fragmentation.
IEEE Access
Mohammad Mehdi Gilanian Sadeghi, Somayeh Timarchi, Mahmood Fazlali
2023 J jnl
Non-Volatile and High-Performance Cascadable Spintronic Full-Adder With No Sensitivity to Input Scheduling.
IEEE Trans. Circuits Syst. II Express Briefs
Mina Raouf, Somayeh Timarchi
2023 J jnl
Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ladan Sayadi, Somayeh Timarchi, Akbar Sheikh-Akbari
2022 J jnl
Area-Time-Efficient Scalable Schoolbook Polynomial Multiplier for Lattice-Based Cryptography.
IEEE Trans. Circuits Syst. II Express Briefs
Yahya Arzani Birgani, Somayeh Timarchi, Ayesha Khalid
2022 J jnl
Efficient Approximate Multiplier Based on a New 1-Gate Approximate Compressor.
Circuits Syst. Signal Process.
Seyed Amir Hossein Ejtahed, Somayeh Timarchi
2022 J jnl
Ultra-lightweight FPGA-based RC5 designs via data-dependent rotation block optimization.
Microprocess. Microsystems
Yahya Arzani Birgani, Somayeh Timarchi, Ayesha Khalid
2021 J jnl
Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ahmad Shabani, Mohammad Sabri Abrebekoh, Bahareh Khabbazan, Somayeh Timarchi
2020 J jnl
Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hossein Mahdavi, Somayeh Timarchi
2019 J jnl
Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hossein Mahdavi, Somayeh Timarchi
2019 J jnl
Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2
Circuits Syst. Signal Process.
Somayeh Timarchi, Negar Akbarzadeh
2019 J jnl
Optimized Parity-Based Error Detection and Correction Methods for Residue Number System.
J. Circuits Syst. Comput.
Adib Armand, Somayeh Timarchi, Hossein Mahdavi
2019 J jnl
Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix.
Microelectron. J.
Ahmad Shabani, Somayeh Timarchi, Hossein Mahdavi
2018 J jnl
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates.
IEEE Trans. Very Large Scale Integr. Syst.
Hamed Naseri, Somayeh Timarchi
2017 J jnl
Low-power DCT-based compressor for wireless capsule endoscopy.
Signal Process. Image Commun.
Ahmad Shabani, Somayeh Timarchi
2016 J jnl
An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques.
Circuits Syst. Signal Process.
Majid Moghaddam, Somayeh Timarchi, Mohammad Hossein Moaiyeri, Mohammad Eshghi
2016 J jnl
Efficient modulo 2
Int. J. Comput. Aided Eng. Technol.
Masoud Abbasi Alaie, Somayeh Timarchi
2016 — conf
Ultra-low voltage standard cell libraries: Design strategies and a case study.
ICECS
Somayeh Timarchi, Massimo Alioto
2015 J jnl
Fast architecture for decimal digit multiplication.
Microprocess. Microsystems
Mahmood Fazlali, Hadi Valikhani, Somayeh Timarchi, Hadi Tabatabaee Malazi
2014 — conf
High-speed energy-efficient 5: 2 compressor.
MIPRO
Ardalan Najafi, Somayeh Timarchi, Amir Najafi
2013 C conf
High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding.
VLSI-SoC
Somayeh Timarchi, Maryam Saremi, Mahmood Fazlali, Georgi Gaydadjiev
2012 J jnl
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2
IET Comput. Digit. Tech.
Somayeh Timarchi, Mahmood Fazlali
2010 C conf
A unified addition structure for moduli set {2
ICCD
Somayeh Timarchi, Mahmood Fazlali, Sorin Dan Cotofana
2010 J jnl
Efficient Reverse Converter Designs for the New 4-Moduli Sets 2
IEEE Trans. Circuits Syst. I Regul. Pap.
Amir Sabbagh Molahosseini, Keivan Navi, Chitra Dadkhah, Omid Kavehei, Somayeh Timarchi
2009 J jnl
A new algorithm for determining all possible symmetric hybrid redundant numbers.
IEICE Electron. Express
Somayeh Timarchi, Keivan Navi
2009 J jnl
A novel low-power full-adder cell for low voltage.
Integr.
Keivan Navi, Mehrdad Maeen, Vahid Foroutan, Somayeh Timarchi, Omid Kavehei
2009 J jnl
Arithmetic Circuits of Redundant SUT-RNS.
IEEE Trans. Instrum. Meas.
Somayeh Timarchi, Keivan Navi
2009 — conf
Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation.
ISVLSI
Somayeh Timarchi, Keivan Navi, Omid Kavehei
2005 — conf
Evaluation of Some Exponential Random Number Generators Implemented by FPGA.
Parallel and Distributed Computing and Networks
Somayeh Timarchi, Seyed Ghassem Miremadi, Ali Reza Ejlali