Sohan Purohit

21 papers B 1C 1Misc 1Journal 7Unranked 11
YearRankTypeTitle / Venue / Authors
2014 J jnl
Designing Dynamic Carry Skip Adders: Analysis and Comparison.
Circuits Syst. Signal Process.
Raffaele De Rose, Marco Lanuzza, Fabio Frustaci, Sohan Purohit
2013 J jnl
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
2013 J jnl
Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede
2012 J jnl
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance.
IEEE Trans. Very Large Scale Integr. Syst.
Sohan Purohit, Martin Margala
2011 — conf
A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks.
HPCS
Wim Vanderbauwhede, Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala
2010 — conf
A C++-embedded Domain-Specific Language for programming the MORA soft processor array.
ASAP
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
2010 C conf
An area efficient design methodology for SEU tolerant digital circuits.
ISCAS
Sohan Purohit, David Harrington, Martin Margala
2010 J jnl
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder.
J. Low Power Electron.
Sohan Purohit, Marco Lanuzza, Martin Margala
2010 — conf
Design of self correcting radiation hardened digital circuits using decoupled ground bus.
ACM Great Lakes Symposium on VLSI
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
2010 — conf
Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths.
AHS
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
2010 — conf
Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems.
AHS
Mohamed El-Hadedy, Sohan Purohit, Martin Margala, Svein J. Knapskog
2010 J jnl
Radiation-Hardened Reconfigurable Array With Instruction Roll-Back.
IEEE Embed. Syst. Lett.
Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
2009 — conf
A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic.
ACM Great Lakes Symposium on VLSI
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala
2009 B conf
A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model.
FPL
Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit, Martin Margala
2009 J jnl
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems.
J. Low Power Electron.
Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2009 Misc conf
Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath.
VLSI Design
Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2009 — conf
MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor.
AHS
Sai Rahul Chalamalasetti, Sohan Purohit, Martin Margala, Wim Vanderbauwhede
2009 — conf
New performance/power/area efficient, reliable full adder design.
ACM Great Lakes Symposium on VLSI
Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello
2009 — conf
Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor.
ERSA
Wim Vanderbauwhede, Martin Margala, Sai Rahul Chalamalasetti, Sohan Purohit
2008 — conf
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices.
ReConFig
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello
2008 — conf
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing.
SoCC
Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello