Sneh Saurabh

25 papers C 2Misc 7Journal 12Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
Fault-Tolerant Design Framework for Probabilistic-Bit (P-Bit) Systems: Proposal and Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Amina Haroon, Sneh Saurabh
2025 J jnl
LiMo: A Framework Leveraging Machine Learning for Multi-Input Switching Timing Models of Complex Logic Gates.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pooja Beniwal, Sneh Saurabh, N. Vignesh Chowdary, Suriya Skariah, Ajoy Mandal, Ramakrishnan Venkatraman
2025 J jnl
Skyrmion-based synaptic element with strain-mediated plasticity.
Neuromorph. Comput. Eng.
Jasmine Kaur, Sneh Saurabh, Shubham Sahay
2024 Misc conf
Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement.
VLSID
Pooja Beniwal, Sneh Saurabh
2024 Misc conf
FLIP: An Artificial Neural Network-based Post-routing Incremental Placer.
VLSID
Pranav Jain, Gagandeep, Sneh Saurabh
2024 J jnl
Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Amina Haroon, Ram Krishna Ghosh, Sneh Saurabh
2024 Misc conf
Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis.
VLSID
Shivendra Singh, Ekta Tiwari, Abhinav Gupta, Sneh Saurabh
2023 J jnl
Deep Neural Network Augmented Wireless Channel Estimation for Preamble-Based OFDM PHY on Zynq System on Chip.
IEEE Trans. Very Large Scale Integr. Syst.
Syed Asrar Ul Haq, Abdul Karim Gizzini, Shakti Shrey, Sumit Jagdish Darak, Sneh Saurabh, Marwa Chafii
2023 Misc conf
Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and Analysis.
VLSID
Amina Haroon, Ram Krishna Ghosh, Sneh Saurabh
2022 C conf
A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking.
VLSI-SoC
Raiyyan Malik, Shubham Baunthiyal, Puneet Kumar, Srinath J, Sneh Saurabh
2022 J jnl
Deep Neural Network Augmented Wireless Channel Estimation on System on Chip.
CoRR
Syed Asrar Ul Haq, Abdul Karim Gizzini, Shakti Shrey, Sumit Jagdish Darak, Sneh Saurabh, Marwa Chafii
2022 Misc conf
Image Completion using a Sparse Probabilistic Spin Logic Network.
VLSID
Amina Haroon, Sneh Saurabh
2022 J jnl
Muller C-Element Exploiting Programmable Metallization Cell for Bayesian Inference.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Jasmine Kaur, Sneh Saurabh, Shubham Sahay
2021 — conf
An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network.
MLCAD
Madhvi Agarwal, Sneh Saurabh
2021 J jnl
Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis.
IEEE Access
Mamidala Karthik Ram, Neha Tiwari, Dawit Burusie Abdi, Sneh Saurabh
2021 J jnl
Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-State Current of Short Channel MOSFETs: A TCAD Study.
IEEE Access
Mamidala Karthik Ram, Neha Tiwari, Dawit Burusie Abdi, Sneh Saurabh
2021 J jnl
Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
O. V. S. Shashank Ram, Sneh Saurabh
2021 C conf
Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate-Source Underlap.
VLSI-SoC
Akshay Balaji, Sneh Saurabh
2020 — conf
Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate.
VDAT
Subhadip Poria, Shelly Garg, Sneh Saurabh
2019 — conf
Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean Function.
ISQED
Vaibhav Agarwal, Sneh Saurabh
2019 J jnl
Dopingless 1T DRAM: Proposal, Design, and Analysis.
IEEE Access
Akhil James, Sneh Saurabh
2019 J jnl
Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis.
IEEE Access
Shelly Garg, Sneh Saurabh
2019 Misc conf
Realizing Boolean Functions Using Probabilistic Spin Logic (PSL).
VLSID
Vaibhav Agarwal, Sneh Saurabh
2018 Misc conf
A Practical Methodology to Compress Technology Libraries Using Recursive Polynomial Representation.
VLSID
Sneh Saurabh, Priyanka Mittal
2018 — conf
Assessing the Impact of Temperature and Supply Voltage Variations in Near-threshold Circuits using an Analytical Model.
ACM Great Lakes Symposium on VLSI
Sneh Saurabh, Vishav Vikash