Siying Feng

16 papers A* 4A 2B 3Journal 3Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET.
IEEE J. Solid State Circuits
Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw
2023 J jnl
Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher.
CoRR
Yichen Yang, Jingtao Li, Nishil Talati, Subhankar Pal, Siying Feng, Chaitali Chakrabarti, Trevor N. Mudge, Ronald G. Dreslinski
2022 — conf
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET.
VLSI Technology and Circuits
Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw
2022 — —
Acceleration Techniques of Sparse Linear Algebra on Emerging Architectures
Siying Feng
2022 A* conf
MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows.
ISCA
Siying Feng, Xin He, Kuan-Yu Chen, Liu Ke, Xuan Zhang, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2022 B conf
Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor.
PACT
Xin He, Kuan-Yu Chen, Siying Feng, Hun-Seok Kim, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge
2021 A* conf
CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics.
DAC
Siying Feng, Jiawen Sun, Subhankar Pal, Xin He, Kuba Kaszyk, Dong-Hyeon Park, John Magnus Morton, Trevor N. Mudge, Murray Cole, Michael F. P. O'Boyle, Chaitali Chakrabarti, Ronald G. Dreslinski
2021 A* conf
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.
MICRO
Subhankar Pal, Aporva Amarnath, Siying Feng, Michael F. P. O'Boyle, Ronald G. Dreslinski, Christophe Dubach
2020 J jnl
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits
Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
2020 — conf
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework.
IISWC
Subhankar Pal, Kuba Kaszyk, Siying Feng, Björn Franke, Murray Cole, Michael F. P. O'Boyle, Trevor N. Mudge, Ronald G. Dreslinski
2020 A conf
Sparse-TPU: adapting systolic arrays for sparse matrices.
ICS
Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge
2020 B conf
Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.
PACT
Subhankar Pal, Siying Feng, Dong-Hyeon Park, Sung Kim, Aporva Amarnath, Chi-Sheng Yang, Xin He, Jonathan Beaumont, Kyle May, Yan Xiong, Kuba Kaszyk, John Magnus Morton, Jiawen Sun, Michael F. P. O'Boyle, Murray Cole, Chaitali Chakrabarti, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski
2019 — conf
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
VLSI Circuits
Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski
2019 B conf
Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective.
ISPASS
Siying Feng, Subhankar Pal, Yichen Yang, Ronald G. Dreslinski
2018 A* conf
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.
HPCA
Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski
2017 A conf
A carbon nanotube transistor based RISC-V processor using pass transistor logic.
ISLPED
Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski