Siwei Xiang

18 papers Journal 16Unranked 2
YearRankTypeTitle / Venue / Authors
2026 J jnl
An Area-Efficient and Reconfigurable Accelerator for Massive MIMO Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Siwei Xiang, Liyan Liang, Junfeng Wu, Jia Hou, Jiaxing Wang, Yishuo Meng, Jianfei Wang, Chen Yang
2025 J jnl
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow.
IEEE Trans. Very Large Scale Integr. Syst.
Yishuo Meng, Jianfei Wang, Qiang Fu, Jia Hou, Siwei Xiang, Ge Li, Chen Yang
2025 J jnl
A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yishuo Meng, Junfeng Wu, Siwei Xiang, Jianfei Wang, Jia Hou, Zhijie Lin, Chen Yang
2025 J jnl
A Mixed-Mode Acceleration via Sparsity-Adjustable Pruning for Balancing Computation Density in Lightweight CNNs.
IEEE Trans. Very Large Scale Integr. Syst.
Yishuo Meng, Qiang Fu, Jianfei Wang, Siwei Xiang, Jia Hou, Ge Li, Zhijie Lin, Chen Yang
2025 J jnl
A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jianfei Wang, Chen Yang, Yishuo Meng, Fahong Zhang, Jia Hou, Siwei Xiang, Yang Su
2025 J jnl
A Self-Organizing Linked Storage Architecture With Dynamic Partition Achieving High Capacity Utilization.
IEEE Trans. Circuits Syst. II Express Briefs
Siwei Xiang, Yu Gao, Yishuo Meng, Jianfei Wang, Ge Li, Zhijie Lin, Chen Yang
2025 J jnl
An Efficient CNN Accelerator Exploiting Novel Tile-Based Near-Structured Sparsity to Achieve Multi-Level Irregularity Elimination.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yishuo Meng, Chen Yang, Qiang Fu, Jianfei Wang, Siwei Xiang, Ge Li, Li Geng
2025 J jnl
Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yishuo Meng, Jianfei Wang, Siwei Xiang, Jia Hou, Zhijie Lin, Kuizhi Mei, Chen Yang
2024 J jnl
A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jianfei Wang, Chen Yang, Fahong Zhang, Yishuo Meng, Siwei Xiang, Yang Su
2024 J jnl
A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Jianfei Wang, Chen Yang, Fahong Zhang, Jia Hou, Yishuo Meng, Siwei Xiang, Yang Su
2024 J jnl
ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach.
IEEE Trans. Circuits Syst. II Express Briefs
Yishuo Meng, Siwei Xiang, Jianfei Wang, Jia Hou, Chen Yang
2024 J jnl
Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen Yang, Yaoyao Yang, Yishuo Meng, Kaibo Huo, Siwei Xiang, Jianfei Wang, Li Geng
2024 J jnl
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Chen Yang, Yishuo Meng, Jiawei Xi, Siwei Xiang, Jianfei Wang, Kuizhi Mei
2023 J jnl
A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access.
IEEE Trans. Very Large Scale Integr. Syst.
Chen Yang, Junfeng Wu, Siwei Xiang, Liyan Liang, Li Geng
2023 J jnl
An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow.
IEEE Trans. Very Large Scale Integr. Syst.
Yishuo Meng, Chen Yang, Siwei Xiang, Jianfei Wang, Kuizhi Mei, Li Geng
2023 — conf
An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method.
ICTA
Yuheng Xia, Yishuo Meng, Siwei Xiang, Jianfei Wang, Chen Yang
2023 J jnl
POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection.
Inf.
Jia Hou, Jingyu Zhang, Qi Chen, Siwei Xiang, Yishuo Meng, Jianfei Wang, Cimang Lu, Chen Yang
2021 — conf
A High Performance and Full Utilization Hardware Implementation of Floating Point Arithmetic Units.
ICECS
Chen Yang, Siwei Xiang, Jiaxing Wang, Liyan Liang